Power Module Package Layout for Low-Inductance Die Scaling
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Solution Overview
Problem
Existing power semiconductor device packages face challenges in reducing parasitic impedances such as stray inductance and material costs, while also requiring efficient scaling for different numbers of semiconductor die.
Innovation Solution
A power module package design featuring a substrate with a ceramic layer and patterned metal layers, where high-side and low-side semiconductor die are linearly arranged along parallel axes, coupled with conductive clips and power terminals, and signal pins, allowing for efficient use of substrate space and straightforward scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power semiconductor device packages are used, then parasitic impedances such as stray inductance are reduced, but material costs increase and scaling efficiency decreases
Solution Approach 1:
The package design segments the semiconductor die into high-side and low-side groups arranged in parallel linear arrays, with each group connected to dedicated power terminals. This segmentation allows independent optimization of current paths for each group, reducing parasitic impedance while maintaining manufacturing efficiency through standardized modular arrangements.
Solution Approach 2:
The invention transitions from conventional two-dimensional layouts to a three-dimensional arrangement where semiconductor die are stacked and connected via conductive clips that extend vertically through the package. This dimensional change creates shorter current paths and reduces stray inductance while improving space utilization and scaling efficiency.
2Productivity
If substrate space is optimized for linear arrangement of semiconductor die, then manufacturing efficiency improves, but parasitic impedance reduction becomes more difficult
Solution Approach 1:
The invention merges the functions of power terminals and signal terminals into a unified package structure where both types of terminals are integrated along the edges of the substrate. This consolidation allows for optimized current paths that reduce parasitic impedance while maintaining the linear arrangement of semiconductor die for manufacturing efficiency.
Solution Approach 2:
Conductive clips serve as intermediary elements that connect the linearly arranged semiconductor die to the power terminals. These clips create direct electrical pathways that minimize inductance while allowing the semiconductor die to maintain their space-efficient linear configuration on the substrate.
3Adaptability or versatility
If power terminals are arranged on one edge and signal pins on other edges, then package scalability improves, but current path optimization becomes more complex
Solution Approach 1:
The package design employs universal edge-mounted terminal structures that can accommodate different numbers and types of power and signal terminals along the edges. This universal approach enables easy scaling of the package while maintaining consistent current path geometry, simplifying the optimization process across different package configurations.
Data Source
AI summary
In a general aspect, a power module package includes a substrate that has a ceramic layer with a first primary surface and a second primary surface opposite the first primary surface. The substrate also includes a patterned metal layer disposed on the first primary surface. The package also includes a first plurality of semiconductor die disposed on a first portion of the patterned metal layer. The first plurality of semiconductor die are linearly arranged along a first axis. The package further includes a second plurality of semiconductor die disposed on a second portion of the patterned metal layer. The second plurality of semiconductor die are linearly arranged along a second axis parallel to the first axis.