Power Semiconductor Module Stack for Smaller Substrates and Cooling
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Solution Overview
Problem
Power semiconductor module arrangements face challenges in efficiently dissipating heat from controllable semiconductor elements while minimizing the required substrate size, leading to increased costs and space requirements.
Innovation Solution
A power semiconductor module arrangement featuring a substrate with a dielectric insulation layer and distinct metallization sections, where an additional metallization layer is positioned parallel and distant from the primary metallization layer, reducing the need for substrate size and allowing efficient heat dissipation through the dielectric insulation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the substrate size is reduced to minimize space requirements, then space and cost are improved, but heat dissipation capability deteriorates
Solution Approach 1:
The patent transitions from a planar heat dissipation approach to a three-dimensional structure by adding a vertically extending heat dissipation element that rises from the substrate surface. This vertical dimension allows heat to be dissipated away from the substrate plane, enabling effective thermal management in a reduced footprint substrate area.
Solution Approach 2:
The heat dissipation function is segmented from the substrate itself into a separate, dedicated heat dissipation element. This allows the substrate to be minimized for its primary electrical function while the heat dissipation element handles thermal management, resolving the contradiction between substrate size and heat dissipation capability.
2Ease of manufacture
If the substrate size is reduced to minimize costs, then manufacturing cost is improved, but heat dissipation efficiency deteriorates
Solution Approach 1:
By extending heat dissipation into the vertical dimension through a dedicated heat dissipation element, the patent enables efficient thermal management in a compact substrate, reducing the substrate area and associated manufacturing costs while maintaining heat dissipation performance.
3Area of stationary object
If metallization layers are positioned closer together to reduce substrate size, then space is improved, but electrical insulation reliability may deteriorate
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary between the first metallization layer and the heat dissipation element. This dielectric layer provides reliable electrical insulation while allowing the heat dissipation element to be positioned in close proximity to the metallization layers, thus reducing substrate size without compromising insulation reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the substrate size and enhances heat dissipation from semiconductor elements, minimizing costs and space requirements while maintaining efficient operation.
Implementation Method 1
heat that is generated during operation of the power semiconductor module arrangement is efficiently dissipated away from the controllable semiconductor elements and the substrate
Data Source
Figure 1~2B
Figure 3A~4
Figure 5A~5B
AI summary
A power semiconductor module arrangement comprises a substrate comprising a dielectric insulation layer and a first metallization layer arranged on a first side of the dielectric insulation layer, wherein the first metallization layer comprises a plurality of different sections that are separate and distinct from each other, and a plurality of semiconductor bodies arranged on the first metallization layer, wherein a first electrode of each of the plurality of semiconductor bodies is electrically coupled to a first section of the first metallization layer, a second electrode of each of the plurality of semiconductor bodies is electrically coupled to a second section of the first metallization layer, a third electrode of each of the plurality of semiconductor bodies is electrically coupled to an additional metallization layer by means of one or more electrical connection elements, the additional metallization layer is arranged distant from and in parallel to the first metallization layer, and the additional metallization layer is arranged on an additional dielectric insulation layer, wherein the additional dielectric insulation layer is arranged in parallel to and distant from the dielectric insulation layer, and wherein the additional dielectric insulation layer is arranged between the additional metallization layer and the first metallization layer.