Power Semiconductor Module Substrate for Low-Inductance EMI Grounding

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Solution Overview

Problem

Power semiconductor devices in power electronics applications experience common-mode electromagnetic interference (EMI) due to the formation of a stray capacitor between the devices and the heat sink, which is exacerbated by high-frequency interconnection stray inductance, leading to suboptimal performance of existing Y-capacitor connection approaches.

Innovation Solution

A power semiconductor module with a substrate featuring an electrically insulative material, metallization layers, and an electrical conductor that connects the metallization layers to reduce interconnection stray inductance, allowing for improved Y-capacitor connection to ground, thereby minimizing impedance at high frequencies and enhancing common-mode EMI suppression.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If a thin electrical isolation layer is used between power semiconductor devices and heat sink, then thermal conductivity is improved, but coupling/stray capacitor impedance decreases leading to increased common-mode EMI

Engineering Contradiction:
Improvethermal conductivityVSAvoidcommon-mode EMI
Core Design Contradiction:
TemperatureVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary electrical isolation layer (ceramic or polymer material) between the power semiconductor devices and heat sink. This layer serves dual purposes: providing thermal conduction path while maintaining electrical isolation to control coupling capacitor impedance. The intermediary material allows optimization of thermal performance without directly compromising EMI performance, as its dielectric properties can be independently selected.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the physical and electrical parameters of the isolation layer by selecting materials with specific thermal conductivity and dielectric constant values. By adjusting the thickness and material composition of the electrical isolation layer, the design optimizes the trade-off between thermal management (requiring thin, high-conductivity material) and EMI suppression (requiring controlled capacitance through material selection).

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If Y-capacitor is connected directly around power semiconductor devices and heat sink, then interconnection stray inductance is reduced, but lack of proper heat sink connection point results in suboptimal performance

Engineering Contradiction:
Improveinterconnection stray inductanceVSAvoidcommon-mode EMI suppression performance
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent transitions from a two-dimensional surface connection approach to a three-dimensional integrated connection by incorporating the Y-capacitor connection directly into the substrate structure. The electrical conductor extending through the substrate creates a vertical connection path that integrates the Y-capacitor connection point with both the power semiconductor device region and the heat sink mounting surface, optimizing both low-inductance performance and thermal connection.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent merges the Y-capacitor connection function with the substrate structure itself. Instead of treating the Y-capacitor connection as a separate external component, the electrical conductor integrated into the substrate combines the electrical isolation, Y-capacitor connection, and heat sink mounting functions into a single unified structure, achieving optimal performance for both EMI suppression and thermal management.

Inventive Principle:
Principle #5Merging (Combining)

3Object-affected harmful factors

If electrical conductor connects second metallization layer to frontside, then Y-capacitor connection point is enabled reducing stray inductance, but substrate structure complexity increases

Engineering Contradiction:
Improvestray inductanceVSAvoidsubstrate structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The electrical conductor in the substrate serves multiple functions simultaneously: it provides the Y-capacitor connection point, enables low-inductance electrical path, maintains structural integrity of the substrate, and facilitates heat dissipation. This multi-functional design reduces the need for additional separate components or structures, thereby minimizing overall complexity while achieving the desired EMI suppression performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces common-mode ground current and improves EMI bypass performance by minimizing stray inductance and impedance, particularly in the 30 MHz to 1 GHz frequency range, leading to enhanced electromagnetic compatibility.

Implementation Method 1

an electrical conductor disposed in the opening and connected to the part of the second metallization layer exposed by the opening, wherein the electrical conductor enables a point of electrical contact for the second metallization layer

Methodology Applied
Scientific EffectElectrical Conduction: Conduction (electrical)

Implementation Method 2

a substrate comprising an electrically insulative material, a first metallization layer at a frontside of the electrically insulative material, and a second metallization layer at a backside of the electrically insulative material

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 3

The thin electrical isolation layer between the power semiconductor devices and the heat sink acts as the capacitor dielectric

Methodology Applied
Scientific EffectDielectric: Dielectric

Implementation Method 4

the electrical isolation layer should be thin with good thermal conductivity to ensure adequate heat transfer from the power semiconductor devices to the heat sink

Methodology Applied
Scientific EffectThermal Conduction: Conduction (thermal)

Data Source

PatentUS20240170418A1Power semiconductor module and method of producing a power semiconductor module
Publication Date: 2024.05.23 INFINEON TECHNOLOGIES AG
  • US20240170418A1 patent drawing
  • US20240170418A1 patent drawing
  • US20240170418A1 patent drawing

AI summary

A power semiconductor module includes: a substrate having an electrically insulative material, a first metallization layer at a frontside of the electrically insulative material, and a second metallization layer at a backside of the electrically insulative material; a first power semiconductor die of a power electronics circuit; an opening in the electrically insulative material that exposes part of the second metallization layer from the electrically insulative material; and an electrical conductor disposed in the opening and connected to the part of the second metallization layer exposed by the opening. The first power semiconductor die is attached to the first metallization layer at the frontside of the electrically insulative material, or is embedded in the electrically insulative material. The electrical conductor enables a point of electrical contact for the second metallization layer at the frontside of the electrically insulative material. Additional power semiconductor modules and methods of production are described.