Power Module Gate Resistance Balancing for SiC Current Imbalance
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Solution Overview
Problem
In power modules and converters with semiconductor chips connected in parallel, current imbalance leads to increased heat generation and potential chip destruction due to degraded device characteristics, especially in high-temperature environments, where SiC chips are prone to stacking faults and increased resistance.
Innovation Solution
The implementation of a power module design where semiconductor chips with built-in diodes and transistors are electrically connected in parallel, with gate electrodes connected to gate resistances, where the gate resistance for chips with lower current values is greater than those with higher current values when a predetermined voltage is applied, to balance current distribution and reduce heat generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If semiconductor chips are connected in parallel to increase power capacity, then the power capacity is improved, but current imbalance occurs leading to increased heat generation and potential chip destruction
Solution Approach 1:
The patent applies local quality by assigning different gate resistance values to different semiconductor chips based on their individual characteristics. Specifically, chips with smaller current values are connected to larger gate resistances, while chips with larger current values are connected to smaller gate resistances. This localized adjustment of electrical parameters ensures balanced current distribution across all parallel-connected chips, preventing current concentration and heat generation in specific chips while maintaining overall high power capacity.
2Reliability
If gate resistance is increased to balance current distribution, then current balance is improved, but switching speed decreases
Solution Approach 1:
The patent resolves this contradiction by applying local quality through differentiated gate resistance assignment. Instead of using a uniform gate resistance for all chips, the invention connects each chip to a gate resistance value tailored to its current characteristics. Chips requiring current balancing receive higher gate resistances, while chips with better current characteristics receive lower gate resistances to maintain switching speed. This localized optimization achieves both current balance and acceptable switching performance across the parallel-connected chip array.
Data Source
AI summary
An object of the present invention is to increase the reliability of a power module and a power converter and to extend their life. In order to achieve this, a power module includes: two switching devices each including a diode and a transistor, the two switching devices being electrically connected in parallel; and an insulating substrate on which the two switching devices are mounted. Further, a gate electrode of MOFET that each of the two switching device has is electrically connected to a gate resistance. Further, of the two switching devices, the gate resistance that is electrically connected to the switching device, whose current value is smaller when a predetermined voltage is applied in the forward direction of the body diode, is greater than the gate resistance that is electrically connected to the switching device whose current value is larger.