Parallel-Chip Power Module Wiring for Low-Noise Gate Drive
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Solution Overview
Problem
Existing power semiconductor modules face challenges in high-density mounting of compound semiconductor chips due to lower chip yield and differences in gate drive voltage and noise voltage, leading to reduced efficiency and reliability.
Innovation Solution
A power semiconductor module design with an insulated substrate featuring parallel and angled bonding wires connecting gate and source electrodes directly to control terminals, eliminating intermediate conductive patterns, and placing conductive patterns in parallel to reduce loop inductance and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple compound semiconductor chips are mounted in parallel on an insulated substrate to achieve predetermined rated current, then the rated current capability is improved, but the module volume increases due to larger wiring area requirements
Solution Approach 1:
The patent transitions from planar wiring patterns on the substrate surface to three-dimensional wire bonding, allowing connections to be made in the vertical dimension above the substrate. This enables multiple chips to be connected with minimal lateral space occupation, reducing the module footprint while maintaining high current capability through parallel chip configuration.
Solution Approach 2:
The insulated substrate serves multiple functions: it provides mechanical support for mounting multiple chips, acts as an electrical insulator between different potential regions, and serves as a platform for wire bonding connections. This multi-functionality reduces the need for additional components and structural elements, compacting the overall module volume.
2Area of stationary object
If wire bonding is used to connect gate electrodes of multiple segments, then the area occupied by gate electrode terminal is decreased, but noise voltage increases due to larger loop area
Solution Approach 1:
The patent uses vertical wire bonding to connect gate electrodes, moving the connection path from the substrate plane to the vertical dimension. This creates compact, tightly-coupled current loops with minimal enclosed area, significantly reducing the magnetic loop area that generates noise voltage during switching operations.
Solution Approach 2:
The patent strategically positions wire bonds to create overlapping current paths that generate opposing magnetic fields during switching. These opposing fields cancel each other out, converting what would normally be noise-generating loops into noise-reducing configurations. The wire bonding structure itself becomes the solution to the noise problem it initially creates.
3Ease of manufacture
If conventional wiring patterns are used on the insulated substrate, then electrical connections are established, but the mounting density of semiconductor chips is reduced due to wiring area occupation
Solution Approach 1:
The patent moves electrical connections from the two-dimensional substrate surface to the three-dimensional space above it using wire bonding. This eliminates the need for large wiring patterns on the substrate surface, freeing up area for chip mounting and enabling higher chip density while maintaining all necessary electrical connections.
Solution Approach 2:
The patent extracts the wiring function from the substrate plane and implements it separately through wire bonding. This separation allows the substrate to be dedicated primarily to chip mounting, while connections are established through a different mechanism that occupies minimal space on the substrate surface itself.
Data Source
AI summary
There is provided a power semiconductor module with multiple semiconductor chips arranged in parallel on an insulated substrate, allowing for high density mounting of semiconductor chips and highly reliable with less difference in operating characteristics from one semiconductor chip to another. The above module includes an insulated substrate; a first conductive pattern laid out on the insulated substrate; multiple power semiconductor chips arranged on the first conductive pattern; a first wiring formed to bridge and directly connecting respective gate electrodes of the power semiconductor chips; and a second wiring formed to bridge and directly connecting respective source electrodes of the power semiconductor chips, wherein the first wiring is placed alongside of the second wiring and may be angled within 30 degrees with respect to the second wiring.