Non-insulated Power Module Groove Insulation

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Solution Overview

Problem

Non-insulated power modules face a challenge in securing both an adequate insulation distance and chip mounting area, as existing structures that provide insulation between die pads and heat radiation fins often reduce the chip mounting area.

Innovation Solution

The solution involves forming first grooves on the lower surface of the package between die pads, allowing for a longer insulation distance with an insulating member, while the trapezoidal cross-sectional shape of the die pads ensures a larger upper surface area for chip mounting, maintaining the area even with groove formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a recess is provided on the lower surface of the package to secure insulation distance, then the insulation distance between die pad and heat radiation fins is improved, but the chip mounting area of the die pad is reduced

Engineering Contradiction:
Improveinsulation distanceVSAvoidchip mounting area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention transitions from a 2D planar insulation approach to a 3D multi-level structure by providing grooves on the lower surface of the package. This allows the insulating member to be positioned in a recessed area, creating vertical separation between the die pad and heat radiation fins while preserving the horizontal chip mounting area on the die pad upper surface.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The lower surface of the package is segmented into functional zones: areas with grooves for insulation purposes and areas without grooves for heat radiation. This segmentation allows different regions to serve different functions - the grooved regions provide insulation while the non-grooved regions maintain thermal coupling with the heat radiation fins.

Inventive Principle:
Principle #1Segmentation

2Reliability

If grooves are formed on the lower surface of the package between die pads, then dielectric tolerance is improved, but the area available for chip mounting is reduced

Engineering Contradiction:
Improvedielectric toleranceVSAvoidchip mounting area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The grooves are provided locally in specific areas of the package lower surface, particularly in regions where insulation is most critical for dielectric tolerance. The chip mounting areas on the die pad upper surfaces are left unaffected, maintaining full mounting capability while providing localized insulation enhancement where needed.

Inventive Principle:
Principle #3Local quality

3Reliability

If the lower surface area of die pads is reduced to accommodate insulation structures, then insulation distance is secured, but the upper surface chip mounting area is compromised

Engineering Contradiction:
Improveinsulation distanceVSAvoidchip mounting area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The insulation structure is implemented in the vertical dimension through grooves on the lower surface, completely decoupling the insulation function from the horizontal chip mounting area. The die pad maintains its full upper surface area for chip mounting while the lower surface grooves provide the necessary insulation distance without affecting the mounting capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11264312B2Non-insulated power module
Publication Date: 2022.03.01 MITSUBISHI ELECTRIC CORP
  • US11264312B2 patent drawing
  • US11264312B2 patent drawing
  • US11264312B2 patent drawing

AI summary

An object of the present invention is to achieve both securing an insulation distance and securing a chip mounting area in a non-insulated power module. A non-insulated power module includes a plurality of die pads, a plurality of semiconductor chips mounted on upper surfaces of the plurality of die pads, and a package sealing the semiconductor chips, in which lower surfaces of the plurality of die pads are exposed from a lower surface of the package, on the lower surface of the package, first grooves are formed in areas between the plurality of die pads, and the plurality of die pads have a trapezoidal cross-sectional shape in the thickness direction, in which an area of an upper surface is larger than an area of the lower surface.