Power Semiconductor Module Layout for Isolated DC and AC Routing
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Solution Overview
Problem
Existing power semiconductor modules have complex internal circuit layouts with messy wiring terminal arrangements, leading to structural complexity and a challenging manufacturing process.
Innovation Solution
A power semiconductor module design that includes a substrate divided into multiple areas, with DC+ and DC- liner plates and an AC liner plate arranged in a compact manner to minimize interference and facilitate wiring, while eliminating the need for bonding structures caused by split copper layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the internal circuit layout uses a split copper structure with bonding connections, then the electrical connectivity is achieved, but the structural complexity and manufacturing process complexity increase significantly
Solution Approach 1:
The patent merges the DC+ and DC- copper layers into a single integrated copper structure without bonding connections. The DC+ and DC- circuits are routed through the same copper layer, eliminating the need for separate bonded copper layers and reducing structural complexity while maintaining electrical connectivity.
Solution Approach 2:
The patent segments the copper layer into different functional regions within the same layer - DC+ regions, DC- regions, and AC regions - allowing each to be independently routed and connected without requiring bonding between separate copper layers, thus simplifying the overall structure.
2Reliability
If the copper layers are arranged in a conventional manner, then the electrical connections are established, but the manufacturing process becomes complex and difficult
Solution Approach 1:
The patent combines multiple copper layers that would traditionally require bonding into a single copper layer structure. This integration eliminates the bonding process step, significantly simplifying the manufacturing process while ensuring reliable electrical connections through the unified copper structure.
3Power
If the liner plates are arranged to maximize electrical connectivity, then the current-carrying capacity increases, but the risk of short circuit between positive and negative electrodes increases
Solution Approach 1:
The patent applies local quality by creating distinct DC+ and DC- regions within the copper layer, with each region optimized for its specific function. The DC+ regions are spatially separated from DC- regions, and isolation structures are placed at critical interfaces, allowing high current capacity in each region while preventing short circuits between opposite polarity regions.
4Volume of moving object
If the circuit layout is designed for compactness, then the power density increases, but the wiring becomes more complex and interference between electrodes increases
Solution Approach 1:
The patent merges DC+ and DC- routing into a single copper layer, eliminating the need for complex inter-layer bonding connections. This integration reduces wiring complexity while maintaining compact dimensions, as the unified copper structure provides direct pathways for both DC+ and DC- circuits without requiring additional bonding layers.
Data Source
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AI summary
The present application provides a power semiconductor module (100), which relates to the field of electrical component technology. The power semiconductor module (100) includes a substrate (110), a DC+ liner plate (111), a DC- liner plate (113), and an AC liner plate (115). The substrate (110) is divided into multiple areas, and mutually isolated the DC+ liner plate (111), the DC- liner plate (113), and the AC liner plate (115) are disposed on a surface of the substrate (110). Compared to the related art, in the power semiconductor module (100) of the present application, the DC+ liner plate (111), the DC- liner plate (113), and the AC liner plate (115) can be reasonably arranged without interfering with one another, which facilitates wiring. Furthermore, the risk of the short circuit is reduced due to the minimized interference between the positive electrode and the negative electrode.