Vehicle Power Module Layout for Low Parasitic Inductance

The patent transitions from planar layout to three-dimensional vertical stacking of semiconductor chips and lead frames. By utilizing the Z-axis dimension, the current path is shortened significantly as connections are made directly above/below components rather than requiring lateral routing, thereby reducing parasitic inductance despite structural constraints in the XY-plane.

The patent implements a nested configuration where semiconductor chips are stacked vertically with lead frames interlaced between layers. The lower lead connects through intermediate layers, creating a compact nested structure that minimizes the current path length while maintaining all necessary electrical connections, thus reducing parasitic inductance within limited structural space.

The patent groups semiconductor components with the same potential difference (equipotential components) adjacent to each other on the circuit board. This arrangement eliminates the need for insulation distances between components at the same potential, thereby minimizing the circuit board area. The layout complexity is managed through systematic potential-based zoning of components.

The patent merges components that share the same potential reference into adjacent positions, consolidating their spatial requirements. By combining the placement of multiple components at the same potential level, the design eliminates redundant insulation spaces and reduces overall circuit board footprint, while the merged layout simplifies the routing of common potential lines.