Power Semiconductor Module Layout for Ultra-Low Inductance
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Solution Overview
Problem
Conventional power semiconductor modules have inductivities that are too high, especially when using fast switching power transistor technologies like SiC MOSFETs, leading to increased switching losses and reduced thermal efficiency.
Innovation Solution
A power semiconductor module design with vertically stacked power transistor dies and overlapping DC busbars, along with auxiliary heat pathways, to achieve ultra-low inductivity and improved thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional power semiconductor module design is used, then manufacturing is simpler, but inductivity is too high (above 700 pH) causing increased switching losses
Solution Approach 1:
The patent transitions from conventional planar bus bar arrangement to a three-dimensional vertically stacked configuration. The DC bus bars are positioned vertically above each other with minimal spacing, and the AC bus bar connects them vertically, creating a compact 3D current loop that dramatically reduces inductivity to below 700 pH while managing the increased structural complexity through systematic spatial organization.
Solution Approach 2:
The patent implements a nested arrangement where the AC bus bar is positioned within the vertical space between the two DC bus bars. The power transistor dies are stacked vertically with the AC bus bar connecting their source terminals in between them, creating a compact nested structure that minimizes the current loop area and reduces inductivity without requiring additional lateral space.
2Speed
If fast switching power transistor dies (SiC MOSFETs) are used, then switching speed increases, but switching losses increase due to high inductivity
Solution Approach 1:
The patent changes the geometric parameters of the bus bar arrangement to achieve ultra-low inductivity. By reducing the loop area through vertical stacking and minimizing spacing between DC bus bars to less than 10mm, the inductivity parameter is reduced to below 700 pH, enabling fast switching SiC MOSFETs to operate with minimal switching losses despite their high switching speeds.
3Loss of energy
If chip embedded technology is used, then inductivity is reduced to about 700 pH, but further reduction is needed for increased efficiency
Solution Approach 1:
The patent moves beyond planar chip embedding to a three-dimensional vertically stacked architecture. The DC bus bars are arranged vertically with minimal spacing, and the AC bus bar connects them in the vertical dimension, creating a compact current loop that achieves inductivity below 700 pH, surpassing conventional chip embedded technology while maintaining manufacturing feasibility.
Data Source
AI summary
A power semiconductor module includes an AC bus bar having a first side that faces a first substrate and a second side that faces a second substrate. A first power transistor die has a drain terminal connected to a first metallic region of the first substrate and a source terminal connected to the first side of the AC bus bar. A second power transistor die has a drain terminal connected to the second side of the AC bus bar and a source terminal connected to a first metallic region of the second substrate. First and second DC bus bars are connected to the first metallic region of the respective substrates, vertically overlap one another, and protrude from a first side of a mold body that encapsulates the power transistor dies. The AC bus bar protrudes from a different side of the mold body as the DC bus bars.