Power Semiconductor Module Packaging for Low-Inductance Heat Dissipation
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Solution Overview
Problem
Traditional power semiconductor module packaging faces challenges with low heat dissipation efficiency, low power density, large parasitic inductance, and high voltage stress, which affect electrical performance and reliability.
Innovation Solution
A novel packaging structure featuring an insulating radiating fin with inner and outer metal conducting layers, a metal lead frame unit, and a chip unit, where high-density metal bonding leads are used for ultrasonic welding, and a plastic package body encases the components to enhance heat dissipation and reduce parasitic inductance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional packaging structure is used with copper wire or aluminum wire bonding, then manufacturing cost is reduced, but parasitic inductance and resistance increase
Solution Approach 1:
The patent replaces traditional wire bonding (mechanical/electrical connection) with direct metal layer-to-chip contact. The inner metal conducting layer is in direct contact with the chip's bottom surface, eliminating the need for bonding wires and thereby reducing parasitic inductance and resistance while maintaining electrical connection functionality.
Solution Approach 2:
The patent extracts and eliminates the bonding wire component from the traditional packaging structure. By removing the bonding wire layer and establishing direct contact between the inner metal conducting layer and chip, the design simplifies the structure and reduces parasitic elements.
2Power
If power semiconductor module volume is increased to achieve higher power density, then power density is improved, but heat dissipation requirements and installation complexity increase
Solution Approach 1:
The patent merges the substrate and heat sink into a single integrated radiating fin structure. The radiating fin serves dual functions as both the mounting substrate for the chip and the heat dissipation component, eliminating the need for separate heat sinks and reducing installation complexity while maintaining high power density.
Solution Approach 2:
The radiating fin structure performs multiple functions simultaneously: it serves as the mechanical substrate for chip mounting, the electrical connection path through metal layers, and the thermal management component for heat dissipation. This multi-functionality reduces overall system complexity.
3Reliability
If traditional packaging with insulating gaskets and thermally conductive coatings is used, then thermal contact resistance is improved, but heat dissipation efficiency and chip impact resistance are reduced
Solution Approach 1:
The patent removes insulating gaskets and thermally conductive coatings from the traditional packaging structure. By eliminating these intermediate layers, the design achieves direct thermal and mechanical contact between the chip and radiating fin, improving both heat dissipation efficiency and chip impact resistance while maintaining acceptable thermal contact resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The novel packaging structure optimizes chip loading area, increases rated current, enhances heat capacity, reduces parasitic inductance and resistance, and decreases voltage stress, thereby improving output power, safety, and reliability while maintaining efficient heat dissipation.
Implementation Method 1
a signal portion of the chip unit is connected with the frame pin signal portion through a metal bonding lead by ultrasonic bonding
Data Source
AI summary
The invention discloses a novel packaging structure of a power semiconductor module, which mainly comprises an insulating radiating fin, a metal lead frame unit and a chip unit. The insulating radiating fin comprises an insulating layer, and an inner metal conducting layer and an outer metal conducting layer which are respectively arranged on two sides of the insulating layer; the metal lead frame unit mainly comprises a frame pin input portion, a frame pin output portion and a frame pin signal portion, the frame pin input portion is arranged on an upper side of the inner metal conducting layer in a solder welding mode, and the chip unit is welded to the middle of the inner metal conductive layer. The frame pin output portion is provided with an inner concave portion.