Power Semiconductor Module Layout for Low-Inductance Switching
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Solution Overview
Problem
Parasitic inductances in power semiconductor modules cause voltage overshoots during fast switching, potentially exceeding the maximum breakdown voltage and leading to device damage.
Innovation Solution
A power semiconductor module design featuring encapsulated power semiconductor dies connected to power leads and pins, with a driver board incorporating capacitors to form a commutation loop, reducing inductance and minimizing current overshoots.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If fast switching is implemented using SiC or GaN semiconductor dies, then switching speed is improved, but parasitic inductances cause voltage overshoots that may exceed breakdown voltage and damage the device
Solution Approach 1:
The power leads are divided into multiple segments (first power lead and second power lead) that are spatially separated and routed through different paths. This segmentation reduces the parasitic inductance in the commutation loop by minimizing the loop area, thereby reducing voltage overshoots during fast switching while maintaining high switching speeds with SiC or GaN dies
Solution Approach 2:
The invention transitions from a planar layout to a three-dimensional configuration by arranging power leads and semiconductor dies in multiple layers and spatial positions. The power leads extend in different directions and are connected at multiple points, creating a compact 3D structure that reduces parasitic inductance while enabling fast switching operation
2Reliability
If parasitic inductances are reduced to minimize voltage overshoots, then device reliability is improved, but the commutation loop area must be minimized which complicates the module design
Solution Approach 1:
The invention combines multiple functions into the power lead structure: electrical connection, mechanical support, and parasitic inductance reduction. The power leads serve both as current carriers and as elements that define the commutation loop geometry, merging structural and electrical functions to reduce complexity while improving reliability
Solution Approach 2:
The power lead structure performs multiple roles simultaneously: providing electrical connections, defining the commutation loop path, and minimizing parasitic inductance through its geometric configuration. This multi-functionality reduces the need for additional components and simplifies the overall module design while ensuring device reliability
Data Source
AI summary
A power semiconductor module includes: an encapsulation body having a first side, an opposite second side, and lateral sides connecting the first and second sides; a first and a second power lead exposed from a first one of the lateral sides, the first power lead configured to provide a first DC+ connection and the second power lead configured to provide a first DC− connection; a plurality of power semiconductor dies encapsulated by the encapsulation body and connected to the first and second power leads; and a first and a second pin exposed from the encapsulation body and arranged perpendicular to the first and second power leads, the first pin configured to provide a second DC+ connection and the second pin configured to provide a second DC− connection.