3D Power Semiconductor Module Layout for Low-Inductance Parallel Chips
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Solution Overview
Problem
Existing power semiconductor modules with GaN or SiC chips face challenges in reducing the area occupied on substrates and minimizing wiring inductance, leading to unstable gate waveforms due to increased inductance and spacing requirements for insulation withstand voltage, especially when multiple chips are connected in parallel.
Innovation Solution
A power semiconductor module configuration with two insulation substrates and conductors with spacer functions that electrically connect semiconductor switching elements, reducing the area occupied and inductance by optimizing the arrangement of electrodes and inter-conductor wiring, thereby stabilizing gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple power semiconductor chips are connected in parallel on a substrate, then the current capacity is satisfied, but the area occupied on the substrate increases
Solution Approach 1:
The patent utilizes three-dimensional vertical arrangement by stacking multiple insulation substrates (first insulation substrate, second insulation substrate) with semiconductor switching elements positioned between them. This vertical stacking approach allows multiple chips to be connected in parallel while minimizing the horizontal substrate area occupation, directly resolving the contradiction between current capacity and substrate area.
2Ease of operation
If wiring length is increased to connect gate electrodes, then gate control is achieved, but wiring inductance increases causing unstable gate waveforms
Solution Approach 1:
The patent segments the gate electrode connections by providing individual gate electrodes on each insulation substrate that can be independently connected to gate input terminals. This segmentation allows for optimized wiring paths that minimize inductance while maintaining gate control functionality, resolving the contradiction between ease of operation and reliability.
Solution Approach 2:
The patent transitions from planar wiring to three-dimensional wiring by routing gate electrodes vertically between the first and second insulation substrates. This vertical arrangement shortens the wiring path and reduces loop area, thereby minimizing wiring inductance and stabilizing gate waveforms while maintaining gate control capability.
3Reliability
If spacing between conductive patterns is increased for insulation withstand voltage, then insulation reliability is improved, but the area occupied increases
Solution Approach 1:
The patent moves insulation from a two-dimensional planar spacing approach to a three-dimensional vertical arrangement. By positioning semiconductor switching elements vertically between the first and second insulation substrates, the patent achieves adequate insulation distance without increasing horizontal spacing, thus maintaining insulation reliability while minimizing substrate area.
Data Source
AI summary
The provided power semiconductor module is configured to reduce the wiring inductance and save space on the substrate by establishing a multi-parallel connection between multiple power semiconductor chips. It consists of a first and second insulated substrates with a plurality of semiconductor switching elements positioned on one and facing the other. There are also first and second spacer conductors positioned between the plurality of semiconductor switching elements and the second insulated substrate. Inter-spacer-conductor wiring parts are connected with the plurality of second spacer conductors. Each of the plurality of semiconductor switching elements has a first electrode connected to a conductor layer on the first substrate, a second electrode connected to a conductor on the second substrate via the first spacer conductors, and a control electrode connected to each other through the second spacer conductors and the inter-spacer-conductor wiring parts which are positioned a prescribed distance from the second conductor layer.