Semiconductor Power Module Layout for Balanced Parallel Switching
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Solution Overview
Problem
Semiconductor power modules for hybrid and electric vehicles face increased electrical losses due to smaller supply lines and higher currents, leading to asymmetrical electrical properties and limited short circuit capability when power transistors are connected in parallel.
Innovation Solution
The semiconductor power module adapts the effective inductances and ohmic resistances of parallel power transistors via specific line routing, ensuring symmetrical control voltages and uniform switching, allowing equal energy distribution and maximum thermal utilization during normal operation and short circuits, while also improving cooling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If power transistors are connected in parallel with asymmetrical line routing to reduce installation space, then installation space is reduced, but electrical losses increase and short circuit capability is limited
Solution Approach 1:
The patent applies asymmetry in reverse - it deliberately creates symmetrical line routing connections for parallel power transistors. The line routing is designed so that both transistors have identical connection paths to the collector and emitter strips, ensuring equal inductance and resistance values. This symmetrical design equalizes current distribution during normal operation and during short circuit conditions, reducing electrical losses while maintaining compact installation space.
2Volume of moving object
If power transistors are connected in parallel with asymmetrical line routing, then installation space is reduced, but short circuit capability is limited
Solution Approach 1:
The patent uses symmetrical line routing design where both parallel power transistors have identical electrical connection paths to the collector and emitter strips. This ensures equal inductance and resistance values for both transistors, enabling balanced current sharing during short circuit events. The symmetry in line routing allows both transistors to contribute equally to short circuit current handling, thereby improving short circuit capability while maintaining reduced installation space.
3Volume of moving object
If line routing is optimized for compact installation, then installation space is reduced, but electrical symmetry is compromised
Solution Approach 1:
The patent deliberately implements symmetrical line routing connections for parallel power transistors within a compact module design. The connection paths from each transistor to the collector and emitter strips are designed to have equal lengths and identical trace patterns, ensuring equal inductance and resistance values. This symmetrical electrical design maintains electrical symmetry while achieving compact installation space through efficient layout optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution results in uniform switching behavior, optimal energy distribution, and enhanced thermal management, enabling better cooling and reduced electrical losses in semiconductor power modules.
Implementation Method 1
The patent applies symmetrical line routing to equalize the effective inductances and ohmic resistances of parallel power transistors, ensuring uniform current distribution and switching behavior
Implementation Method 2
The patent utilizes thermal conduction through collector strip conductors to dissipate heat from power transistors, improving thermal management
Data Source
AI summary
A semiconductor power module including first and second power transistors situated in parallel between first collector and first emitter strip conductors. A first connection surface of each of the power transistors is electroconductively connected to the first collector strip conductor, and a second connection surface of each of the power transistors is electroconductively connected to the first emitter strip conductor, so that a current flowing between the first collector strip conductor and the first emitter strip conductor is divided between the power transistors when the power transistors are each conductively connected via an applied control voltage. A first external power contact is directly contacted with the first collector strip conductor at a first contact area, a second external power contact is contacted with the first emitter strip conductor at a second contact area via a first connecting element, and the second contact area is positioned asymmetrically between the power transistors.