High-Temperature Power Module Parasitic Equalization
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Solution Overview
Problem
Conventional power modules using silicon-based semiconductors are limited by power density, efficiency, and reliability at high temperatures above 175°C and high switching speeds, particularly when utilizing silicon carbide (SiC) devices.
Innovation Solution
A four-quadrant power module with a multi-substrate layout for equalized electrical parasitic power conduction, novel interconnection schemes, and high-temperature materials, enabling operation up to 250°C, simultaneous control of multiple devices, and modular configurations for high-speed switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power packages are used with silicon carbide devices, then high voltage blocking capability and high speed switching are achieved, but reliability deteriorates at temperatures higher than 175°C
Solution Approach 1:
The patent changes the material parameters by replacing conventional packaging materials with high-temperature compatible materials, including high-temperature epoxy molding compounds, high-temperature solder alloys, and ceramic substrates. This allows the power module to maintain reliability at junction temperatures up to 250°C by ensuring all packaging materials can withstand these elevated temperatures without degradation.
Solution Approach 2:
The patent employs composite material structures combining multiple high-temperature resistant materials: ceramic substrates for mechanical support and thermal management, high-temperature epoxy for encapsulation, and specialized thermal interface materials. This composite approach creates a packaging system that maintains structural integrity and electrical performance at temperatures exceeding 175°C.
2Power
If many paralleled power devices are used to increase power density, then power handling capability is improved, but electrical parasitic power distribution becomes unequal
Solution Approach 1:
The patent implements equipotential power distribution by designing symmetrical power paths from the DC link through each paralleled device to ground. All devices share identical electrical characteristics including trace width, trace length, via counts, and component values, ensuring equal current sharing and equalized electrical parasitics across all parallel devices.
Solution Approach 2:
The patent segments the power distribution into identical modular paths for each paralleled device. Each device has its own dedicated return path and gate drive path with matched impedance and parasitic values. This segmentation into equal modules simplifies the achievement of equalized electrical characteristics while scaling power handling capability.
3Loss of energy
If multiple paralleled devices are switched simultaneously to reduce switching losses, then efficiency is improved, but switching synchronization becomes difficult
Solution Approach 1:
The patent applies equipotential principles to gate drive paths by ensuring all gate resistors, gate inductors, and trace impedances are matched across paralleled devices. This equalizes the turn-on and turn-off times for all devices, enabling simultaneous switching without requiring complex synchronization circuitry or control algorithms.
Solution Approach 2:
The patent uses identical gate drive circuitry and component values for each paralleled device, creating duplicate gate drive paths with matched characteristics. This copying approach ensures that all devices respond identically to the same gate signal, achieving simultaneous switching through replication rather than active synchronization.
4Power
If the entire package width is used for power conduction to increase current capacity, then power density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the wide power conduction path into multiple parallel traces distributed across the substrate width. Each trace carries a portion of the total current, and the segmentation is achieved through standard PCB fabrication processes. This approach increases current capacity by utilizing the entire package width while maintaining manufacturability through modular trace design.
Solution Approach 2:
The substrate design serves multiple functions simultaneously: it provides mechanical support, thermal management pathways, electrical isolation, and power conduction across the entire width. By integrating these functions into a single multi-layer substrate structure, the design achieves high current capacity without proportionally increasing manufacturing complexity.
Data Source
AI summary
A four quadrant power module with lower substrate parallel power paths and upper substrate equidistant clock tree timing utilizing parallel leg construction in a captive fastener power module housing.