High-Frequency Power Module Layout to Cut Parasitic Inductance

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Solution Overview

Problem

As operating frequencies increase, parasitic inductance and capacitance from bonding wires in power modules significantly impact circuit performance, necessitating a reduction or elimination of these effects.

Innovation Solution

A power module design with a shortened signal path is achieved by embedding a third base board with conductor layers into a first base board, using insulating materials and conductive structures to electrically connect a power chip, and forming conductive wiring layers with metal layers to reduce parasitic effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If bonding wires are used for interconnection between power chip and lead frames, then manufacturing cost is reduced and connection robustness is improved, but parasitic inductance and parasitic capacitance increase significantly at high frequencies

Engineering Contradiction:
Improvemanufacturing costVSAvoidparasitic inductance and parasitic capacitance
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent removes bonding wires from the interconnection structure entirely, replacing them with a direct integrated circuit board connection. The power chip is mounted directly on the circuit board with electrical connections made through soldering or other direct bonding methods to contact pads on the board, eliminating the bonding wire component that generates parasitic effects.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from a three-dimensional bonding wire connection (wire extending through space between chip and lead frame) to a planar two-dimensional connection on the circuit board surface. The electrical connections are made through contact pads and conductive traces on the board plane, fundamentally changing the geometric dimension of the interconnection path.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Strength

If bonding wires are used for interconnection, then connection robustness is improved, but signal path length increases causing performance degradation at high frequencies

Engineering Contradiction:
Improveconnection robustnessVSAvoidsignal path length
Core Design Contradiction:
StrengthVSLength of moving object

Solution Approach 1:

The bonding wire is extracted from the interconnection path, replacing the long three-dimensional wire route with a short planar trace on the circuit board. This dramatically reduces the signal path length while maintaining connection integrity through direct mounting and soldering connections.

Inventive Principle:
Principle #2Taking out (Extraction)

3Device complexity

If conventional power module design with bonding wires is used, then manufacturing simplicity is maintained, but circuit performance deteriorates due to parasitic effects at high frequencies

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidcircuit performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent adopts a planar integrated design where the power chip is mounted directly on the circuit board with electrical connections made through contact pads and conductive traces on the board plane. This two-dimensional layout eliminates the need for bonding wires while reducing parasitic effects and improving high-frequency performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12489076B2Power module for high-frequency use and method for manufacturing the same
Publication Date: 2025.12.02 BOARDTEK ELECTRONICS CORP
  • US12489076B2 patent drawing
  • US12489076B2 patent drawing
  • US12489076B2 patent drawing

AI summary

A high-frequency power module less vulnerable to parasitic phenomena includes first base board, power chip, and second base board. The first base board includes a first substrate, a first conductive wiring layer, and a second conductive wiring layer on each side of the first substrate. The power chip is disposed on the first conductive wiring layer. The second base board includes a second substrate covering the power chip and the first conductive wiring layer, and a third conductive wiring layer away from the first conductive wiring layer. First conductive structures penetrate the second substrate to connect the third conductive wiring layer with the power chip, greatly reducing the lengths of signal paths between components and so parasitic effects A second conductive structure penetrates the first and second substrates to connect the first, second, and third conductive wiring layers. A manufacturing method is also disclosed.