Power Module Chip Package With Planar Lead Frame and Protective Layer
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Solution Overview
Problem
Traditional chip packages using Cu clips and wire bonds face challenges such as bulky size, difficulty in achieving thin profiles, die cracking due to heavy weight, and inferior electrical and thermal performance, particularly in power modules.
Innovation Solution
A chip package with an embedded lead frame and protective layer, featuring a metal unit with connection pads, encapsulated by a molding layer, to enhance electrical and thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional Cu clips are used in chip packages, then electrical connection is achieved, but the package becomes bulky and difficult to achieve thin profiles
Solution Approach 1:
The patent transitions from traditional three-dimensional Cu clip structures to a two-dimensional planar lead frame structure. The lead frame is flattened and integrated into the package substrate, eliminating the vertical height occupied by traditional Cu clips while maintaining electrical connection functionality through planar trace routing.
Solution Approach 2:
The patent extracts the essential electrical connection function from the bulky Cu clip structure and reimplements it through a simplified lead frame system. The lead frame is separated into distinct functional elements (connection pads, traces, and mounting structures) that can be optimized independently, removing the unnecessary bulk of traditional Cu clip assemblies.
2Reliability
If Cu clips with heavy weight are attached onto dies, then electrical connection is provided, but the dies may crack due to heavy weight
Solution Approach 1:
The patent fundamentally changes the weight parameter of the connection structure by replacing dense Cu clip materials with a lighter lead frame construction. The lead frame uses thinner traces and a more efficient structural design that reduces overall mass while maintaining mechanical strength and electrical conductivity, thereby preventing die cracking from excessive weight.
Solution Approach 2:
The patent employs composite construction in the lead frame, combining different metal layers and materials with optimized properties. The lead frame may include copper traces on a flexible substrate or multi-layer composite structures that provide both mechanical support and electrical connection with minimized weight, avoiding the stress-induced cracking seen with heavy Cu clips.
3Reliability
If wire bonds are used for connection, then electrical connection is achieved, but electrical and thermal performance becomes inferior
Solution Approach 1:
The patent merges the electrical connection and thermal management functions into a single integrated lead frame structure. Unlike wire bonds that require separate pathways for electrical and thermal conduction, the lead frame provides both functions through its solid, continuous metal traces that simultaneously conduct electricity and dissipate heat efficiently, improving overall system performance.
Solution Approach 2:
The patent replaces the mechanical wire bond system with an integrated planar electrical connection system. The lead frame uses direct metal-to-metal contact and solid trace routing instead of suspended wire bonds, eliminating the mechanical vulnerabilities of wire bonding while providing superior electrical conductivity and thermal pathways through the solid-state construction.
Data Source
AI summary
The present disclosure provides a chip package for power modules including at least one semiconductor die; a driver circuit for controlling the at least one semiconductor die; a protective layer formed on a die active surface of the at least one die and a driver active surface of the driver circuit; a metal unit having at least one metal feature; and a molding layer for encapsulating the at least one semiconductor die, the driver circuit, the protective layer and metal unit. The chip package is connected with an external circuit via the at least one metal feature. The present disclosure also provides a method of making the chip packages for power modules.