Double-Faced Power Module Spacer Current Distribution

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Solution Overview

Problem

Existing power modules with double-faced cooling suffer from non-uniform current application to semiconductor chips, which can damage specific chips due to current concentration, and this issue is not effectively addressed for next-generation semiconductors like SiC or GaN.

Innovation Solution

The use of spacers that electrically connect the upper and lower substrates at equal distances from semiconductor chips ensures uniform current distribution by guiding currents through a layered structure of spacers and substrates, preventing concentration on individual chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If multiple semiconductor chips are disposed between upper and lower substrates in a double-faced cooling power module, then cooling efficiency is improved and size is reduced, but current uniformity deteriorates causing chip damage

Engineering Contradiction:
Improvecooling efficiencyVSAvoidcurrent uniformity
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent introduces spacers as intermediary elements between the upper substrate and lower substrate. These spacers serve as current distribution mediators that receive current from the upper substrate and distribute it uniformly to multiple semiconductor chips on the lower substrate, preventing current concentration and improving reliability while maintaining the double-faced cooling structure

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the current distribution function by introducing separate spacer elements positioned at specific locations. Instead of direct substrate-to-chip connections, the current path is divided into segments: upper substrate → spacer → semiconductor chip. This segmentation allows independent optimization of current distribution to each chip, ensuring uniformity across all chips

Inventive Principle:
Principle #1Segmentation

2Power

If Si IGBT chip capacity is increased to solve current uniformity issues, then individual chip performance improves, but the solution cannot be applied to next-generation semiconductors like SiC or GaN

Engineering Contradiction:
Improvechip capacityVSAvoidsemiconductor material compatibility
Core Design Contradiction:
PowerVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal current distribution structure using spacers that can be applied to any semiconductor chip type. The spacer-based current distribution mechanism is material-agnostic and can accommodate Si IGBT, SiC, GaN, or future semiconductor technologies without modification, making the solution universally applicable across different semiconductor generations and material systems

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution achieves uniform current application across semiconductor chips, reducing the risk of damage from current concentration and improving the overall balance of current densities, thereby enhancing the reliability of power modules for next-generation semiconductors.

Implementation Method 1

a first spacer disposed between the upper substrate and the lower substrate, electrically connecting the upper substrate and the lower substrate to each other

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS10825763B2Power module of double-faced cooling
Publication Date: 2020.11.03 HYUNDAI MOTOR CO LTD
  • US10825763B2 patent drawing
  • US10825763B2 patent drawing
  • US10825763B2 patent drawing

AI summary

A power module of double-faced cooling includes: an upper substrate; a lower substrate on which a plurality of semiconductor chips are disposed; and a first spacer disposed between the upper substrate and the lower substrate, electrically connecting the upper substrate and the lower substrate to each other, and disposed on the lower substrate to be equally distanced from each of the semiconductor chips. Power is supplied to the semiconductor chips on the lower substrate through the upper substrate and the first spacer.