Power module layout for symmetric switching and temperature sensing

The patent applies asymmetry by intentionally creating asymmetric DC voltage pad geometries and asymmetric interconnect configurations. Specifically, the first DC voltage pad has a different shape and size than the second DC voltage pad, and the interconnect elements connecting to each pad are designed with different characteristics. This asymmetric design allows the system to achieve symmetric switching operation by compensating for inherent imbalances in the physical layout, thereby maintaining power conversion efficiency while reducing the complexity of achieving perfect symmetric commutation loops.

The patent merges the sense connection functionality by implementing a shared sense connection structure. Instead of providing separate sense connections for each transistor die, the design uses common sense pads and shared interconnect paths that allow monitoring of operational states (such as temperature and current) for multiple chips through fewer connection points. This integration maintains measurement precision by capturing essential operational data while significantly reducing the number of discrete sense connections required.

The patent extracts the sense connection functions from individual chip-level connections and consolidates them into substrate-level sense pads and shared interconnect structures. By moving the sense connection points from the chip level to the substrate level, the design reduces the precision requirements for chip-to-substrate alignment while maintaining reliable sensing capabilities. The sense pads are positioned on the substrate where they can be more easily aligned and connected, thereby improving manufacturing feasibility without compromising sensing reliability.