Power Semiconductor Module Layout for Low-Inductance Y-Capacitor Grounding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power semiconductor devices in power electronics applications experience common-mode electromagnetic interference (EMI) due to the formation of a stray capacitor between the devices and the heat sink, which is exacerbated by high-frequency impedance issues in existing Y-capacitor connections, leading to suboptimal noise suppression.
Innovation Solution
The implementation of a Y-capacitor connection approach that minimizes interconnection stray inductance by forming an electrical conductor through an insulative substrate to establish a direct ground connection, reducing the impedance at high frequencies and enhancing EMI bypass performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a thin electrical isolation layer is used between power semiconductor devices and heat sink, then thermal conductivity is improved, but coupling capacitance increases leading to increased common-mode EMI
Solution Approach 1:
The patent introduces an intermediary Y-capacitor connected between the heat sink and AC ground to mediate the coupling capacitance effect. This external Y-capacitor provides a controlled capacitive path that compensates for the unwanted coupling capacitance formed by the thin electrical isolation layer, thereby reducing common-mode EMI while maintaining adequate thermal conductivity.
2Object-affected harmful factors
If a common-mode filter with Y-capacitor is inserted between AC source and power conversion stage, then common-mode EMI is suppressed, but high-frequency impedance increases due to internal ESL and external stray inductance
Solution Approach 1:
The patent connects the Y-capacitor in a different dimensional configuration - directly from the heat sink (chassis ground) to AC ground, bypassing the traditional series path through the common-mode inductor. This dimensional change in connection topology eliminates the external stray inductance and internal ESL from the high-frequency current path, maintaining low impedance at high frequencies while still providing EMI suppression.
3Reliability
If Y-capacitor is connected between power source and AC ground directly around power semiconductor devices, then interconnection stray inductance is reduced, but performance becomes suboptimal due to lack of proper connection point to heat sink
Solution Approach 1:
The patent utilizes the heat sink itself as the connection point for the Y-capacitor. The heat sink, which is already present in the system for thermal management, serves a dual function by providing both heat dissipation and an electrical connection point for the Y-capacitor to chassis ground. This self-service approach eliminates the need for additional connection points or modifications to the power semiconductor devices, making the implementation straightforward while achieving low stray inductance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces common-mode ground current and improves electromagnetic interference suppression by minimizing stray inductance, thereby enhancing the overall performance of power semiconductor modules in the 30MHz to 1GHz frequency range.
Implementation Method 1
an electrical conductor disposed in the opening and connected to the part of the second metallization layer exposed by the opening, wherein the electrical conductor enables a point of electrical contact for the second metallization layer
Implementation Method 2
The thin electrical isolation layer between the power semiconductor devices and the heat sink acts as the capacitor dielectric. This capacitor is often referred to as a coupling or stray capacitor in noise analysis.
Implementation Method 3
The CM-noise suppression effectiveness of such a common-mode filter depends on, among other things, the impedance of the Y-capacitor compared to the noise source impedance at the frequency range of concern.
Data Source
Figure 1A
Figure 1B
Figure 2A~2C
AI summary
A power semiconductor module includes: a substrate having an electrically insulative material, a first metallization layer at a frontside of the electrically insulative material, and a second metallization layer at a backside of the electrically insulative material; a first power semiconductor die of a power electronics circuit; an opening in the electrically insulative material that exposes part of the second metallization layer from the electrically insulative material; and an electrical conductor disposed in the opening and connected to the part of the second metallization layer exposed by the opening. The first power semiconductor die is attached to the first metallization layer at the frontside of the electrically insulative material, or is embedded in the electrically insulative material. The electrical conductor enables a point of electrical contact for the second metallization layer at the frontside of the electrically insulative material. Additional power semiconductor modules and methods of production are described.