Power MOS Gate Structure with Dual Oxide Thickness and Conductive Bridges
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Solution Overview
Problem
Power electronic MOS devices face challenges in maintaining high-frequency operation reliability due to unbalanced gate resistance across elementary transistors, leading to uneven switch speeds and potential device failure, especially when subjected to high voltage and current gradients.
Innovation Solution
A power MOS device with a gate structure featuring a double thickness oxide region and conductive bridges connecting thicker and thinner oxide portions, ensuring balanced switch times across all transistors, and a method for manufacturing this structure that includes growing a thick oxide layer, etching for central and lateral portions, and depositing conductive layers for bridge formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single thickness oxide layer is used for the gate structure, then the manufacturing process is simpler, but the gate resistance varies across different transistors leading to unbalanced switch speeds
Solution Approach 1:
The patent applies local quality by implementing a gate structure with dual oxide thicknesses: a first oxide layer with thickness T1 over the channel region and a second oxide layer with thickness T2 (where T2 > T1) over the gate mesh region. This local differentiation allows the gate resistance to be balanced across all transistors, ensuring uniform switching performance while maintaining manufacturing feasibility through selective oxide deposition techniques.
2Speed
If the gate mesh resistance is reduced by adding more metal interconnections, then the switching speed improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent changes the physical parameter of oxide thickness in the gate structure to control electrical resistance. By increasing the oxide thickness T2 in the gate mesh region compared to the channel region (T1), the gate resistance is reduced, enabling faster switching speeds. This approach avoids adding complex metal interconnection networks and achieves speed improvement through material parameter optimization rather than structural complexity increase.
3Speed
If the oxide thickness is increased in the gate mesh region, then the gate resistance is reduced improving switching speed, but the manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary action by first depositing the thinner oxide layer T1 over the entire surface, then selectively removing oxide from specific regions to expose the channel, and finally depositing the thicker oxide layer T2 only over the gate mesh region. This sequential approach with preliminary preparation steps enables precise thickness control and reduces manufacturing difficulty compared to attempting to deposit different thicknesses in a single step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a uniform time constant for all elementary MOS transistors, enhancing dynamic performance and reliability by reducing gate resistance variability and preventing current localization issues, thus improving the overall switching performance and lifespan of the device.
Implementation Method 1
growing a thick oxide layer
Implementation Method 2
depositing conductive layers for bridge formation
Data Source
AI summary
Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.