Power MOSFET Trench Layout for Lower On-Resistance
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Solution Overview
Problem
Reducing the pitch of the gate trench in semiconductor devices leads to the laterally expanded column region contacting the gate trench, hindering the current path and increasing on-resistance, which limits the improvement of semiconductor device characteristics.
Innovation Solution
A semiconductor device structure where a third impurity region of the first conductivity type is formed to cover the bottom portion of the gate trench, with a column region of the second conductivity type having a deeper bottom portion than the gate trenches, preventing contact between the column region and the gate trench, and a manufacturing method involving epitaxial growth, ion implantation, and gate insulating film formation to achieve this configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the pitch of the gate trench is reduced to lower on-resistance, then the on-resistance decreases, but the column region contacts the gate trench and hinders the current path
Solution Approach 1:
The invention solves the contradiction by extending the column region in the depth direction (vertical dimension) beyond the gate trench depth, while maintaining adequate horizontal spacing. This dimensional change allows the column region to reach deeper into the drift region without laterally contacting the gate trench, thus maintaining both low on-resistance and reliable current path.
Solution Approach 2:
The invention applies local quality by creating a non-uniform depth profile where the column region extends deeper than the gate trench only in the regions between adjacent gate trenches, while maintaining standard depth under the gate trenches themselves. This localized deepening optimizes current flow paths without compromising the gate trench isolation function.
2Area of stationary object
If the pitch of the gate trench is reduced to minimize chip area, then the chip area decreases, but the column region contacts the gate trench and increases on-resistance
Solution Approach 1:
The invention enables smaller chip area by reducing the horizontal pitch of gate trenches while compensating for the potential contact issue by extending the column region vertically. This allows tighter spacing of gate trenches without increasing on-resistance, thus minimizing chip area while maintaining electrical performance.
Solution Approach 2:
The invention applies preliminary action by pre-positioning the column region to extend deeper than the gate trench before final device operation. This preliminary depth extension prevents future contact issues between the column region and gate trench, enabling aggressive pitch reduction for minimal chip area.
3Manufacturing precision
If ion implantation is used to form the column region, then the column region can be formed with precise doping, but the mask must be miniaturized and impurities diffuse during heat treatment
Solution Approach 1:
The invention applies preliminary action by forming the column region with extended depth before subsequent processing steps. This early formation allows the use of larger, less miniaturized masks while still achieving the desired final geometry through controlled diffusion and selective etching processes.
Solution Approach 2:
The invention utilizes parameter changes by controlling the diffusion of implanted impurities during heat treatment to achieve the desired depth profile. By adjusting temperature, time, and concentration parameters, the column region achieves both precise doping and appropriate depth extension without requiring excessive mask miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for reduced on-resistance and chip area by preventing contact between the column region and the gate trench, even when the pitch of the gate trench is minimized, thereby enhancing semiconductor device performance.
Implementation Method 1
forming a first impurity region of a first conductivity type on the semiconductor substrate by performing an epitaxial growth method
Implementation Method 2
forming a second impurity region of the first conductivity type in the first impurity region so as to cover a bottom portion of the first gate trench by performing ion implantation
Data Source
AI summary
A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.