Power MOSFET Gate Oxide Structure for Better UIS Robustness

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Solution Overview

Problem

The use of stepped gate insulating layers in power MOSFET devices improves switching loss characteristics but deteriorates UIS characteristics, leading to rapid voltage and current spikes that can destroy the device.

Innovation Solution

A power semiconductor device design with a substrate, epitaxial layers, ion implantation regions, and a gate insulating layer structure that includes a channel gate insulating layer and a protruding gate insulating layer, along with a self-aligned ion implantation method to form a second conductivity type ion implantation region with high lateral resistance, improving UIS characteristics by reducing Miller Capacitance and internal base resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a stepped gate insulating layer structure is adopted to reduce oxide capacitance and improve switching loss characteristics, then switching loss is reduced, but UIS characteristics deteriorate due to increased di/dt change amount and rapid voltage and current spikes

Engineering Contradiction:

Improveswitching lossVSAvoidUIS characteristics

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent applies local quality by creating a stepped gate insulating layer structure where the insulating layer thickness varies spatially: a first thickness in the channel formation region and a second (thicker) thickness in other regions. This local variation reduces oxide capacitance in non-channel areas to decrease switching loss while maintaining adequate insulation in the channel region to preserve UIS characteristics and prevent parasitic bipolar operation.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the physical parameter of gate insulating layer thickness to resolve the contradiction. By adjusting the thickness distribution (thinner in channel region, thicker elsewhere), the oxide capacitance is optimized to reduce switching loss while maintaining sufficient insulation to prevent rapid di/dt changes that would deteriorate UIS characteristics.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If the gate insulating layer thickness is reduced to lower oxide capacitance and switching loss, then switching efficiency improves, but the device becomes more susceptible to voltage and current spikes during UIS conditions

Engineering Contradiction:

Improveswitching speedVSAvoidvoltage and current spikes

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The stepped gate insulating layer structure applies local quality by differentiating insulating layer thickness between regions: a first thickness in the channel formation region maintains adequate insulation to suppress voltage and current spikes during UIS, while a second (thicker) thickness in other regions reduces oxide capacitance to improve switching speed and reduce switching loss.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The gate insulating layer is segmented into regions with different thicknesses: a first region over the channel formation area and a second region over other areas. This segmentation allows each region to be optimized independently - the channel region maintains reliability during UIS while other regions contribute to reduced switching loss and improved switching performance.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively reduces switching loss and improves UIS characteristics by lowering the internal base resistance and Miller Capacitance, preventing device destruction from voltage and current spikes.

Implementation Method 1

a second conductivity type ion implantation region partially disposed in the second conductivity type well

Methodology Applied

Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20250022949A1Power semiconductor device, power semiconductor module, power converter including same, and manufacturing method thereof

Publication Date: 2025.01.16 LX SEMICON CO LTD

AI summary

A power semiconductor device includes a substrate, a first conductivity type epitaxial layer disposed on the substrate, a second conductivity type well partially disposed on the first conductivity type epitaxial layer, a second conductivity type ion implantation region partially disposed in the second conductivity type well, a source region partially disposed in the second conductivity type well and disposed on the second conductivity type ion implantation region, a gate insulating layer disposed on the source region and the second conductive type well, a gate disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate, and a source electrode disposed on the source region. The gate insulating layer may include a channel gate insulating layer having a first thickness and a protruding gate insulating layer having a second thickness thicker than the first thickness, A concentration in a Rb region which is a lateral resistance of the second conductivity type ion implantation region may be higher than that of the second conductivity type well.