On-Chip Power Net Resistance Estimation Using ML Regression
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Solution Overview
Problem
Designing on-chip power networks for complex integrated circuits is challenging due to shrinking component sizes and reduced power supply levels, requiring efficient estimation of effective resistance to ensure robust power distribution and identify potential design issues early in the design process.
Innovation Solution
A method using machine learning regression algorithms to quickly estimate effective resistance at nodes in the power network by training models with sampled data, allowing for classification and prediction of resistance values based on statistical characteristics, reducing the need for computationally expensive matrix calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional matrix-based methods are used to calculate effective resistance, then measurement precision is improved, but productivity deteriorates due to long calculation times
Solution Approach 1:
The patent applies preliminary action by pre-training machine learning models offline using comprehensive matrix-based calculations. The trained models capture the relationship between power net topology features and effective resistance values. During actual design analysis, these pre-trained models quickly predict resistance without performing full matrix calculations, thus achieving both accuracy and speed.
Solution Approach 2:
The patent uses copying by creating simplified surrogate models that replicate the behavior of complex matrix-based resistance calculation systems. These surrogate models use power net topology features as inputs and predict resistance values, effectively copying the essential functionality of the original system while operating much faster.
2Measurement precision
If detailed analysis of voltage drop at arbitrary nodes is performed, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the essential information needed for resistance calculation by identifying and using only the relevant power net topology features (such as node connectivity, path lengths, and component distributions) rather than performing complete detailed analysis. This extraction approach reduces complexity while maintaining sufficient accuracy for design decisions.
Solution Approach 2:
The patent substitutes the complex mechanical-like matrix calculation system with a machine learning-based prediction system. The ML models replace the traditional systematic matrix operations with learned patterns from topology features, simplifying the analysis process while maintaining predictive capability.
Data Source
AI summary
Various embodiments of a method and apparatus for estimating the effective resistance for the design of on-chip power nets are disclosed. Through sampled node resistance, performance of a power net can be determined on an entire chip. Effective resistance predictions can be made for all nodes. Through the resistance predictions, a designer can analyze the which areas would benefit from power and ground augmentation.