Power Network Partitioning for Voltage Drop Simulation

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Solution Overview

Problem

Current methods for calculating voltage drop in power networks during timing simulation are cumbersome and CPU-intensive, particularly due to the complexity of combining circuit and power networks, and the traditional RC reduction method suffers from accuracy issues and limitations in handling large sub-networks with many ports.

Innovation Solution

A novel approach that partitions the power network into sub-networks using admittance matrix and voltage transfer in the frequency domain, allowing for larger partition sizes without increasing the number of nodes, and integrates timing simulation in both time and frequency domains with minimal CPU overhead, using algorithms like asymptotic waveform expansion and reduced ordering methods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If RC reduction method is used to simplify power network, then device complexity is reduced, but measurement precision deteriorates

Engineering Contradiction:

Improvepower network complexityVSAvoidvoltage drop calculation accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent transforms the power network representation from time-domain RC circuits to frequency-domain admittance matrices. This parameter transformation allows the network to be represented more compactly while preserving electrical characteristics, thereby reducing complexity without sacrificing accuracy in voltage drop calculations.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces traditional circuit simulation mechanics with frequency-domain mathematical methods. Instead of simulating transient responses through RC time constants, the invention uses admittance matrices and frequency-domain analysis to directly compute voltage drops, achieving both efficiency and accuracy.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Device complexity

If RC reduction is applied to large sub-networks, then device complexity is reduced, but measurement precision deteriorates

Engineering Contradiction:

Improvesub-network reductionVSAvoidaccuracy of large sub-network

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent applies frequency-domain transformation to large sub-networks, converting them into admittance matrix representations. This parameter change allows large networks to be handled efficiently while maintaining accuracy, as the frequency-domain approach captures the electrical behavior without requiring detailed time-domain simulation of every component.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If partition size is increased to reduce number of internal nodes, then productivity is improved, but device complexity increases

Engineering Contradiction:

Improvereduction efficiencyVSAvoidpartition structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent uses frequency-domain admittance matrices to represent partitions, allowing larger partition sizes without proportionally increasing complexity. The matrix-based representation compresses the information about large networks into compact mathematical structures, enabling efficient handling of large partitions.

Inventive Principle:

Principle #35Parameter changes

4Ease of operation

If traditional spice-in-spice-out approach is used, then ease of operation is improved, but measurement precision deteriorates

Engineering Contradiction:

Improvesimulation compatibilityVSAvoidvoltage drop accuracy

Core Design Contradiction:

Ease of operationVSMeasurement precision

Solution Approach 1:

The patent replaces traditional time-domain circuit simulation with frequency-domain analysis. By using admittance matrices and frequency-domain methods, the invention achieves more accurate voltage drop calculations while maintaining ease of operation through systematic mathematical procedures that are well-suited for automated timing verification tools.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10325047B2Power network reduction and simulation in time and frequency domains to calculate voltage drop

Publication Date: 2019.06.18 SAGE SOFTWARE

AI summary

In the present invention the issue of calculating voltage drop at the contact points of the power network with injected power currents is proposed. The method consists of the three steps. First, the said power network is partitioned into sub-networks. Secondly, the said sub-networks are expressed in terms of their admittance matrices and voltage transfer functions, which are then fed into timing simulator handling both time and frequency to compute the voltage drop at the said contact points. To achieve better partition result, inputs, outputs including user assigned nodes for recording voltages, are utilized to absorb the sub-network without inputs and outputs into the same partition as its parent node, and generate output cone with single input and outputs. Timing simulator uses convolution to get input voltage at each time step recursively and then voltage transfer used to evaluate output voltage at the same time step with minimal computational overhead.