Power-On Management Circuit for DRAM Peak Current Control
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Solution Overview
Problem
Existing power-on circuits for DRAMs face issues with peak current exceeding system limits during power-on, leading to potential failure, and existing solutions either fail to manage peak current effectively or extend the power-on sequence beyond JEDEC minimum time requirements.
Innovation Solution
A power-on management circuit with a first and second external power-on voltage detector, a delay unit, logic circuit, internal power-on voltage detector, and multiple electric pumps, where the second voltage threshold is higher than the first, and the logic circuit includes a latch device and logic gates to generate enabling signals that control the activation of electric pumps, distinguishing between fast and slow power-on periods to manage peak current within JEDEC specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all electric pumps are turned on simultaneously during fast power-on period, then power-on speed is improved, but peak current exceeds system limits causing potential failure
Solution Approach 1:
The patent applies preliminary action by detecting external voltage before activating electric pumps. The external power-on voltage detector triggers a sequence where pumps are activated only after voltage confirmation, preventing premature high-current draw while maintaining fast power-on capability through optimized pump control signals.
Solution Approach 2:
The patent implements periodic action through sequential activation of electric pumps using staggered control signals. Instead of simultaneous activation, pumps are turned on in a controlled sequence with defined time intervals, reducing peak current while ensuring all pumps eventually activate during the power-on period.
2Reliability
If electric pumps are turned on sequentially to reduce peak current, then system reliability is improved, but power-on sequence time exceeds JEDEC minimum requirements
Solution Approach 1:
The patent applies dynamics by making the pump activation strategy adaptive based on detected voltage conditions. The control logic dynamically adjusts the activation sequence - enabling faster activation when voltage conditions permit, while maintaining reliable current management when conditions require more conservative sequencing, thus meeting both speed and reliability requirements.
Solution Approach 2:
The patent changes operational parameters by adjusting pump activation timing and sequence based on detected voltage levels and system state. This parameter optimization allows the system to achieve fast power-on when conditions allow while maintaining peak current within limits, satisfying both JEDEC timing requirements and electrical constraints.
3Device complexity
If voltage control circuit activates pumps without precise timing control, then device complexity is reduced, but peak current management becomes ineffective
Solution Approach 1:
The patent introduces intermediary components - external and internal power-on voltage detectors - that mediate between the power source and electric pumps. These detectors provide precise timing signals to the control circuit, enabling effective peak current management without requiring complex control logic, thus maintaining simplicity while achieving reliable current control.
Data Source
AI summary
A power-on management circuit for a memory device is provided. The power-on management circuit comprises a first external power-on voltage detector, a second external power-on voltage detector, a delay unit, a logic circuit, an internal power-on voltage detector, a voltage control circuit, a plurality of first electric pumps and a second electric pump. The first external power-on voltage detector has a first voltage threshold, receives a first external voltage, and generates a first control signal when the first external voltage is higher than the first voltage threshold. The second external power-on voltage detector has a second voltage threshold, receives a second external voltage, and generates a second control signal when the second external voltage is higher than the second voltage threshold.