Power On Reset Circuit Using Delay-Stage and Output-Stage Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional power on reset signal generation circuits face instability due to slow rising speed and noise interference in DC power voltage, leading to unreliable electronic device resets.
Innovation Solution
A noise-immune and power voltage transition speed adaptive circuit using a delay-stage and output-stage configuration with charging and discharging path limiting devices, ensuring the power on reset signal experiences a disactivated state before an activated state and remains stable despite noise or varying power voltage speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional power reset signal generation circuit is used, then the circuit is simple, but the power on reset signal cannot be generated stably when hard powered on due to slow rising speed and noise interference
Solution Approach 1:
The circuit is divided into two independent stages: a delay-stage circuit that generates control voltage signals with disactivated levels, and an output-stage circuit that generates the power on reset signal. This segmentation allows each stage to perform its specific function optimally, with the delay-stage ensuring proper timing and the output-stage ensuring noise immunity, thereby resolving the contradiction between reliability and complexity.
Solution Approach 2:
The patent introduces control voltage signals as an intermediary between the power voltage and the power on reset signal. These control voltage signals act as mediators that translate the power voltage transitions into properly timed and noise-immune reset signals, solving the stability issue without requiring excessive circuit complexity.
2Speed
If the power voltage rises rapidly, then the charging speed is fast, but the power on reset signal stays at low level for a specific time period causing stable reset
Solution Approach 1:
The delay-stage circuit performs preliminary action by generating control voltage signals in advance with disactivated levels before the power on reset signal is generated. This preliminary action ensures that even when power voltage rises rapidly, the control signals are already prepared to enforce the correct timing sequence, preventing premature or unstable reset signal transitions.
Solution Approach 2:
The circuit dynamically adapts to different power voltage rising speeds by using capacitive charging and discharging mechanisms. The delay-stage circuit's capacitors naturally adjust their charging rates based on the input power voltage speed, allowing the circuit to maintain proper timing whether the power voltage rises quickly or slowly, thus resolving the contradiction between speed and timing accuracy.
3Adaptability or versatility
If the power voltage has positive noises, then the voltage fluctuates, but the power on reset signal becomes low again causing unintended reset
Solution Approach 1:
The circuit employs beforehand cushioning by using capacitors in both stages that act as energy reservoirs and filters. These capacitors cushion against voltage fluctuations and noise by maintaining stable voltage levels during transient disturbances, preventing noise from causing unintended reset signal transitions while maintaining the circuit's ability to respond to legitimate power transitions.
Solution Approach 2:
The circuit converts the harmful effect of noise and voltage fluctuations into a benefit by using the same capacitive elements that cause slow charging to also filter noise. The dual-path design with controlled charging and discharging paths allows the circuit to ignore noise-induced voltage variations while still responding correctly to intentional power transitions, turning potential harm into noise immunity.
4Speed
If the power voltage rises slowly, then the charging speed matches the power voltage rise, but the power on reset signal stays directly at high level without experiencing low level period
Solution Approach 1:
The delay-stage circuit performs preliminary action by ensuring control voltage signals reach disactivated levels before triggering the output-stage. This preliminary timing control ensures that even when power voltage rises slowly, the control signals are prepared in advance to enforce the complete low-level period, preventing the reset signal from skipping the required low-level state.
Solution Approach 2:
The circuit uses feedback mechanisms where the control voltage signals continuously monitor the charging status of capacitors and adjust the timing accordingly. This feedback ensures that the power on reset signal only transitions to high level after the control signals confirm the proper low-level period has elapsed, maintaining reliable reset signal transition completeness regardless of power voltage rising speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit ensures a stable power on reset signal generation, preventing unintended resets and maintaining normal operation even with slow rising power voltage speeds or noise presence, thereby ensuring reliable electronic device resets.
Implementation Method 1
the first charging path limiting device receives a direct current (DC) power voltage and charges the first capacitor at the first end thereof with a first charging current to generate a first control voltage signal
Implementation Method 2
the second control voltage signal charges the second capacitor at the first end thereof via the second charging path limiting device when the first control voltage signal has an activated level, the second charging path limiting device outputs a transitional power on reset signal
Data Source
AI summary
Disclosed is an improved circuit and method for generating a power on reset signal, the circuit being a two-stage circuit comprising a delay-stage circuit and an output-stage circuit. The delay-stage circuit delays a time for a power on reset signal generated in the output-stage circuit changing from low to high, so that a power voltage having a low rising speed may be normally reset. Further, the two stages provide charging paths and discharging paths so that the power on reset signal may be prevented from changing from high to low when it has changed from low to high, when noises are presented on the power voltage.