Power-On Reset Circuit With Hysteresis for Stable Chip Initialization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In digital integrated or digital-analog hybrid integrated circuit chips, the absence of a power-on reset circuit leads to uncertain output states of digital logic modules during the power-on process, potentially causing logic confusion or damage, and instability in power supply voltage can result in oscillation of the output reset signal.
Innovation Solution
A power-on reset circuit is designed using a first resistor, a second resistor, a third resistor, a fourth resistor, a first inverter, a second inverter, a first PMOS transistor, a first NMOS transistor, and a clamp device, which adjusts the threshold voltage for the output signal to ensure stable initialization and prevent oscillation through hysteresis feedback.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a power-on reset circuit is not provided, then the chip structure is simpler, but the output states of digital logic modules become uncertain during power-on, causing logic confusion or damage
Solution Approach 1:
The power-on reset circuit performs preliminary initialization of digital logic modules by detecting power-on state and automatically generating reset signals before normal operation begins, ensuring all modules start in a known stable state without requiring manual intervention
Solution Approach 2:
The circuit uses feedback mechanisms through cross-coupled inverters and transistors to continuously monitor the power supply voltage and automatically adjust the reset signal output to maintain stable initialization states during power-on and power-off transitions
2Device complexity
If a simple reset circuit is used, then the device complexity is reduced, but power supply voltage instability causes oscillation of the output reset signal
Solution Approach 1:
The reset circuit employs dynamic threshold voltage control through transistor-based voltage division and clamping mechanisms that automatically adapt to power supply voltage changes, raising the switching threshold during voltage transitions to prevent oscillation while maintaining responsiveness to actual power-on events
Solution Approach 2:
The circuit changes the threshold voltage parameter dynamically based on power supply conditions by using transistor gate-source voltage relationships and resistor ratios to create a moving threshold that prevents reset signal oscillation during unstable power supply periods
Data Source
AI summary
A power-on reset circuit is provided. During a power-on process of the power-on reset circuit, a threshold voltage of an output signal rstn jumping from a low level to a high level is adjusted by clamp of a voltage at a node c and voltage division between a first resistor and a second resistor, and is controlled to be greater than a threshold voltage of a metal oxide semiconductor device. During a power-off process of the power-on reset circuit, a threshold voltage of the output signal rstn jumping from the high level to the low level is adjusted by increasing a voltage at a node d by means of a third resistor and voltage division between the first resistor and the third resistor, and is controlled to be greater than the threshold voltage of the metal oxide semiconductor device.