Power-On Reset Circuit for Semiconductor IC Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing power on reset techniques fail to ensure a stable initial state of semiconductor integrated circuits during power supply turn-on, leading to potential erroneous output operations by external input/output buffer circuits due to incomplete internal initialization.
Innovation Solution
A semiconductor integrated circuit design that includes a power supply detecting circuit and a power on reset circuit, which ensures the external input/output buffer enters an operable state only after the internal circuit initialization is complete, using separate power supply voltages and a system controller to synchronize the initialization process with a clock signal, preventing erroneous output operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the external input/output buffer circuit is enabled early to perform output operation, then the productivity is improved, but the reliability deteriorates due to erroneous output operations when internal circuits are not yet initialized
Solution Approach 1:
The power on reset circuit generates a reset signal that maintains the external input/output buffer circuit in a high impedance state during the initialization period. This preliminary action prevents the buffer from entering an operable state until the internal circuit initialization is complete, thereby avoiding erroneous output operations while enabling productive operation as soon as initialization finishes.
2Reliability
If the power on reset duration is extended to ensure complete internal initialization, then the reliability is improved, but the productivity deteriorates due to delayed output operation
Solution Approach 1:
The power on reset circuit monitors the initialization status of internal circuits through feedback signals. When the system controller completes the initialization of internal circuits, it generates an initialization completion signal that triggers the power on reset circuit to release the reset signal. This feedback mechanism ensures the buffer remains in high impedance state only for the necessary duration, maintaining reliability while minimizing productivity loss.
Data Source
AI summary
The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.