Power-Optimized Design Verification via Combinational Equivalency

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Solution Overview

Problem

Existing equivalency checking methods are inefficient in verifying the functional equivalence of power-optimized digital integrated circuits and their original designs, particularly due to limitations in combinational equivalency checkers that require multiple steps and complex transformations.

Innovation Solution

The implementation of a method using combinational equivalency checking with intermediate design transformations specified through a transformation language, allowing for flexible verification sequences and support for retiming principles, which can handle logic gated and clock gated technologies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Extent of automation

If combinational equivalency checking is used to verify power-optimized designs, then verification automation is improved, but the ability to handle complex design transformations is insufficient

Engineering Contradiction:

Improveverification automationVSAvoidhandling design transformations

Core Design Contradiction:

Extent of automationVSAdaptability or versatility

Solution Approach 1:

The verification process is segmented into multiple stages by introducing intermediate design transformations. Instead of directly comparing the original design with the power-optimized design, the patent breaks down the transformation into a sequence of intermediate steps, each verified separately. This segmentation allows the combinational equivalency checker to handle complex transformations that would otherwise be too difficult to verify in a single step.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Intermediate design transformations are introduced as mediator structures between the original design and the power-optimized design. These intermediates serve as bridge components that facilitate the verification process by providing a step-by-step transformation path. Each intermediate transformation is verified using combinational equivalency checking, making the overall verification process manageable and automated.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If multiple intermediate design transformations are introduced for verification, then functional equivalence can be proven, but verification complexity increases

Engineering Contradiction:

Improvefunctional equivalence proofVSAvoidverification process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The verification process is divided into multiple manageable segments through intermediate design transformations. Each segment represents a specific transformation step that can be verified independently using combinational equivalency checking. This segmentation reduces the complexity of each individual verification task while maintaining the overall reliability of the functional equivalence proof.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The intermediate design transformations are prepared and defined in advance before the actual verification process. By pre-establishing the transformation sequence and its intermediate steps, the verification process becomes more systematic and less complex. The preliminary action of defining transformation rules allows the combinational equivalency checker to proceed with standardized, predictable verification steps.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If combinational equivalency checking is used, then verification speed is improved, but handling of sequential behavior is limited

Engineering Contradiction:

Improveverification speedVSAvoidsequential behavior handling

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent extracts the sequential behavior verification requirements from the overall verification process and handles them through the introduction of intermediate design transformations. By taking out the sequential aspects and addressing them through transformation-based combinational checking, the system maintains high verification speed while adequately handling sequential behavior verification.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces sequential verification mechanisms with combinational equivalency checking mechanisms. Instead of using slow sequential simulation or checking, the system uses faster combinational logic transformations and equivalency checking to verify functional equivalence. This substitution maintains verification accuracy while dramatically improving verification speed.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS8099703B1Method and system for verifying power-optimized electronic designs using equivalency checking

Publication Date: 2012.01.17 XILINX INC

AI summary

Embodiments of the present invention provide methods and systems for verifying functional equivalence of a power optimized design and its original, unoptimized design (referred to as the golden design) using combinational equivalency checking. Due to some inherent limitations which make combinational equivalency checkers unable to prove equivalency of the two designs in a single step, a series of intermediate design transformations is introduced. These transformations are dependent on the techniques used in generating the power optimized design from the golden design, and may be generically described in a transformation language that provides the necessary constructs to specify an entire set of valid structural modifications. The equivalency between the golden design and the power optimized design can then be verified by checking the golden design and the first design transformation, and then by checking between each pair of the plurality of intermediate design transformations, and finally by checking the last design transformation and the power optimized design.