Power Overlay Structure for Symmetric Multi-Chip Gate Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multi-chip semiconductor packages face challenges in maintaining layout symmetry and low inductance interconnects, which are crucial for ensuring good load sharing, minimizing voltage and current overshoots, and reducing switching losses. Additionally, connecting multiple gate pads and source pads to form a common gate and source pad with sufficient surface area for reliable bonding is difficult, especially when dealing with high current power modules that require precise impedance balancing.
Innovation Solution
A multi-chip semiconductor package with an interconnecting power overlay (POL) structure, where an interconnect layer with a dielectric material includes common source and gate pads on its upper surface, and semiconductor devices are adhered to this layer with their source and gate pads electrically connected in parallel. This configuration provides an oversized surface area for complex interconnect configurations and reduces bonding stresses by distributing the connections over a larger area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect gate pads and source pads, then electrical connections can be established, but the layout symmetry and inductance control become difficult to maintain
Solution Approach 1:
The patent replaces wire bonding (mechanical connection) with a planar interconnect layer system using metallization vias and traces. This substitution enables precise control of electrical paths, maintains layout symmetry, and reduces inductance while establishing reliable electrical connections between multiple gate pads and source pads to common pads.
Solution Approach 2:
The patent transitions from two-dimensional wire bonding to a multi-layer planar interconnect structure. By adding vertical dimension with multiple interconnect layers and metallization vias, the system achieves complex routing while maintaining topological symmetry and controlling inductance, thereby improving load sharing among parallel devices.
2Reliability
If the common gate pad and common source pad surface area is increased, then reliable bonding to external circuitry is achieved, but the overall surface area of the multi-chip assembly is limited
Solution Approach 1:
The patent utilizes multiple interconnect layers stacked vertically to increase the effective surface area of common gate and source pads. By extending pads across multiple layers and using metallization vias for vertical connections, the system achieves larger bonding area without increasing the footprint, thereby maintaining bonding reliability within limited assembly area.
Solution Approach 2:
The patent embeds multiple interconnect layers within each other, with lower layers providing additional pad area that is not visible from the top view. The nested structure allows common pads to extend through multiple layers, effectively increasing bonding surface area while maintaining a compact overall assembly footprint.
3Power
If multiple semiconductor devices are paralleled to achieve high current, then current capacity increases, but maintaining impedance balance and simultaneous switching becomes more difficult
Solution Approach 1:
The patent employs symmetric layout design where all parallel devices have identical trace lengths, widths, and via configurations connecting to common pads. This deliberate symmetry ensures equal impedance paths for all devices, enabling simultaneous switching and current sharing. The symmetric geometry compensates for device parameter variations by providing matched external connections.
Solution Approach 2:
The patent designs the interconnect structure to provide equal electrical potential conditions for all parallel devices during switching. By maintaining symmetric impedance paths and equal trace geometries, all device gates experience identical voltage transitions simultaneously, ensuring equipotential operation across parallel devices despite manufacturing variations.
4Ease of manufacture
If direct soldering or copper-bonding is used on small common pads, then bonding is achieved, but bonding stresses are introduced onto the multi-chip assembly
Solution Approach 1:
The patent extends common pads across multiple interconnect layers, providing a distributed bonding area that spreads mechanical stresses vertically and horizontally. This multi-layer pad structure reduces stress concentration on any single bonding interface, thereby protecting the multi-chip assembly from bonding-induced stresses while maintaining ease of manufacturing.
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
A multi-chip semiconductor package (200) includes a dielectric interconnect layer (260) having an upper surface (261) and a bottom surface, at least one common source pad (280) disposed on the upper surface of the interconnect layer, at least one common gate pad (292) disposed on the upper surface of the interconnect layer, and a plurality of semiconductor devices (100) each including a gate pad and at least one source pad adhered onto the interconnect layer, wherein the source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and wherein the source pads of the plurality of semiconductor devices are electrically connected in parallel with one another, and wherein the gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad, and wherein the gate pads of the plurality of semiconductor devices are electrically connected in parallel with one another.