Power Overlay Structure for Symmetric Multi-Chip Package Routing
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Solution Overview
Problem
Existing multi-chip semiconductor packages face challenges in maintaining layout symmetry and low inductance interconnects, which are crucial for ensuring good load sharing, minimizing voltage and current overshoots, and reducing switching losses. Additionally, connecting multiple gate pads and source pads to form a common gate and source pad for external power electronic circuitry is complicated by limited surface area and bonding stresses.
Innovation Solution
A multi-chip semiconductor package with an interconnecting power overlay (POL) structure, featuring an oversized surface area for common gate and source pads, and additional interconnect layers for complex routing configurations. This design includes a redistribution layer (RDL) positioned directly over multiple semiconductor devices, enhancing the available surface area and reducing bonding stresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the surface area of common gate pad and common source pad is increased to improve connection reliability and reduce bonding stresses, then the available surface area for external connections is improved, but the overall surface area of the multi-chip semiconductor assembly is limited
Solution Approach 1:
The patent introduces a power overlay (POL) structure that extends the common gate pad and common source pad onto an additional dimensional plane above the semiconductor devices. This allows the pads to achieve a larger effective surface area for external connections without increasing the footprint of the multi-chip assembly, thereby improving connection reliability while working within the limited available surface area constraint.
2Power
If multiple semiconductor devices are paralleled to achieve high current power modules, then the current handling capability is improved, but the layout symmetry and impedance matching become more complicated
Solution Approach 1:
The patent merges multiple individual device connections to the common gate and source pads through a unified power overlay structure. By combining the interconnect paths into a single overlay layer with symmetric routing, the patent simplifies the layout complexity that would otherwise arise from paralleling multiple devices, while maintaining the high current handling capability through the combined parallel connection of multiple semiconductor devices.
3Reliability
If wire bonds are used to connect gate pads and source pads, then the electrical connections can be established, but the inductance of interconnect increases and load sharing becomes poor
Solution Approach 1:
The patent replaces the mechanical wire bond interconnect system with a planar metallization-based power overlay structure. This substitution eliminates the high inductance associated with wire bonds and complex routing configurations, thereby reducing switching losses and improving load sharing among paralleled devices, while maintaining reliable electrical connections through the low-inductance planar interconnect paths.
Data Source
AI summary
A multi-chip semiconductor package includes a dielectric interconnect layer having an upper surface and a bottom surface, at least one common source pad disposed on the upper surface of the interconnect layer, at least one common gate pad disposed on the upper surface of the interconnect layer, and a plurality of semiconductor devices each including a gate pad and at least one source pad adhered onto the interconnect layer, wherein the source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and wherein the source pads of the plurality of semiconductor devices are electrically connected in parallel with one another, and wherein the gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad, and wherein the gate pads of the plurality of semiconductor devices are electrically connected in parallel with one another.