Wire-Bond-Free Power Semiconductor Package for Dual-Sided Heat Dissipation
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Solution Overview
Problem
Current semiconductor packages face limitations in heat dissipation and ampacity due to ineffective packaging technologies, particularly the use of wire bonds which can be a weak point and restrict the power handling capabilities, and there is a need for improved thermal dissipation paths in power semiconductor devices.
Innovation Solution
The power semiconductor package includes a first and second carrier submount with direct coupling of semiconductor dies without wire bonds, utilizing a flip chip configuration and an insulating layer to enhance thermal dissipation and reduce electrical shorts, and an encapsulating portion to isolate components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If wire bonds are used in semiconductor packages, then electrical connections can be established, but thermal dissipation capability and power handling are limited
Solution Approach 1:
The patent removes wire bonds from the package structure entirely, extracting the problematic element that limited thermal dissipation. Instead of using wire bonds for electrical connections, the invention employs direct bond copper (DBC) or active metal brazed (AMB) substrates with conductive patterns that provide both electrical connectivity and thermal management pathways, eliminating the thermal bottleneck created by wire bonds
Solution Approach 2:
The carrier substrate serves multiple functions simultaneously: it provides mechanical support for the semiconductor die, establishes electrical connections through conductive patterns, and acts as a thermal management system through its thermally conductive structure. This multi-functional integration eliminates the need for separate wire bonds and dedicated thermal pathways, resolving the contradiction between electrical connectivity and thermal dissipation
2Loss of energy
If direct coupling of semiconductor die to carrier submount is implemented, then thermal dissipation paths are enhanced, but manufacturing complexity increases
Solution Approach 1:
The carrier substrate is pre-configured with conductive patterns and thermal management structures before the semiconductor die is attached. The DBC or AMB substrate is manufactured with integrated copper or metal layers that establish both electrical and thermal pathways in advance, simplifying the final assembly process despite the advanced substrate fabrication requirements
Solution Approach 2:
The patent replaces traditional mechanical wire bonding processes with a direct attachment method where the semiconductor die is bonded directly to the carrier substrate using solder or other bonding techniques. This substitution eliminates complex wire bonding equipment and processes while achieving superior thermal and electrical performance through the direct mechanical and thermal coupling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides two thermal dissipation paths for the semiconductor die, increases power handling capabilities, and reduces the risk of electrical shorts, thereby enhancing the performance and reliability of power semiconductor devices.
Implementation Method 1
Each semiconductor die of the plurality of semiconductor die has a first surface and an opposing second surface. Furthermore, for each semiconductor die of the plurality of semiconductor die, the first surface is directly coupled to the first carrier submount, and the second surface is directly coupled to the second carrier submount.
Data Source
AI summary
Semiconductor packages are provided. In one example, a power semiconductor package includes a first carrier submount, a second carrier submount, and a plurality of semiconductor die. Each semiconductor die of the plurality of semiconductor die has a first surface and an opposing second surface. Furthermore, for each semiconductor die of the plurality of semiconductor die, the first surface is directly coupled to the first carrier submount, and the second surface is directly coupled to the second carrier submount.