Power Pick-Up Cell Layout for Buried Power Rail Density
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Solution Overview
Problem
The miniaturization of integrated circuits (ICs) leads to stricter layout design constraints, particularly with buried power rails, limiting the layout area available for standard cells due to forbidden zones occupied by power pick-up cells, which reduces the total layout area for functional circuits.
Innovation Solution
Implementing power pick-up cells with additional logic functions, such as inverters, buffers, NAND gates, and NOR gates, that also serve to connect upper power rails with buried power rails, thereby reducing the number of forbidden zones and increasing the usable layout area by utilizing the power pick-up cells' functionality to alleviate space constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power pick-up cells are used to connect upper power rails with buried power rails, then power delivery is ensured, but the layout area available for standard cells is reduced due to forbidden zones
Solution Approach 1:
The power pick-up cell is designed to perform multiple functions: it connects upper power rails with buried power rails (power delivery function) while simultaneously providing logic functions such as inverter, buffer, NAND gate, or NOR gate. This multi-functionality allows the same cell structure to serve both power distribution and logic operations, thereby reducing the need for separate logic cells and increasing the layout area available for standard cells.
2Area of stationary object
If the layout area for standard cells is increased, then circuit functionality is improved, but power delivery to buried power rails becomes constrained
Solution Approach 1:
By integrating logic functions within the power pick-up cell structure, the invention enables the cell to fulfill both power delivery and logic operation requirements. This eliminates the need to choose between expanding layout area for standard cells or ensuring power delivery, as both functions are achieved simultaneously through the multi-functional power pick-up cell.
3Device complexity
If separate power pick-up cells and logic cells are used, then functional separation is maintained, but device complexity and layout area consumption increase
Solution Approach 1:
The invention merges the power pick-up cell structure with logic cell functionality by integrating inverter, buffer, NAND gate, or NOR gate circuits within the power pick-up cell. This combination reduces the total number of cells required in the layout, thereby decreasing device complexity and reducing the total layout area consumed while maintaining both power delivery and logic functions.
Data Source
AI summary
An integrated circuit includes a first buried power rail, a second buried power rail, a first power pad in a first metal layer, and a first conductive segment beneath the first metal layer. The first buried power rail and the second buried power rail are both located beneath the first metal layer. The first power pad is configured to receive a first supply voltage through at least one first via. The first conductive segment is conductively connected to the first power pad through at least one second via between the first conductive segment and the first metal layer. The first conductive segment is conductively connected to the first buried power rail through at least one third via between the first conductive segment and the first buried power rail.