Embedded Power Pickup Layout for Low-Voltage-Drop CFETs
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Solution Overview
Problem
Existing integrated circuit (IC) designs face challenges in reducing voltage drops due to current flow, particularly in high current operations such as clock circuits, which affect performance and efficiency.
Innovation Solution
The integration of stacked complementary field-effect transistors (CFETs) with metal-like defined (MD) segments and interconnect structures between isolation structures, providing a low resistance reference voltage connection through adjacent conductive lines, thereby reducing voltage drops and enabling higher current operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional IC designs are used, then device miniaturization is achieved, but voltage drops increase due to current flow in high current operations
Solution Approach 1:
The power pickup structure is segmented into multiple components: frontside conductive line, backside conductive line, and intermediate conductive elements (via plugs, contact holes, interconnect structures) that work together to create a distributed low-resistance path, thereby reducing overall voltage drop while maintaining miniaturization
Solution Approach 2:
The patent transitions from planar two-dimensional power distribution to three-dimensional vertical power pickup by stacking conductive elements across frontside, intermediate, and backside layers, creating a multi-layer conductive pathway that reduces resistance without increasing footprint area
2Device complexity
If conventional power distribution is used, then device complexity is reduced, but current handling capability decreases in high driving clock cell applications
Solution Approach 1:
The power pickup employs composite conductive structures combining different materials and geometries (frontside conductive line, via plugs, interconnect structures, backside conductive line) to achieve low resistance and high current handling capability while managing structural complexity through integrated design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances IC performance by minimizing voltage drops and enabling higher current operations, particularly in high driving clock cell applications.
Implementation Method 1
a conductive structure extending from the first conductive line to the second conductive line... providing a low resistance reference voltage connection... reducing voltage drops
Data Source
AI summary
An IC device includes two isolation structures extending in parallel in a first direction in a front side of a semiconductor substrate, a stacked CFET circuit including gates and metal-like defined (MD) segments extending in the first direction between the isolation structures. Each of the gates extends from first to second locations along the first direction and one of the MD segments is configured as a reference voltage connection of the circuit and extends from the first location to a third location further along the first direction than the second location. Frontside and backside conductive lines extend in a second direction perpendicular to the first direction, and a conductive structure extends from the frontside conductive line to the backside conductive line along a third direction perpendicular to each of the first and second directions and includes a portion of the MD segment between the second and third locations.