Power Profile Control Using Real-Time Current Throttling

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Solution Overview

Problem

Current methods for monitoring and throttling power consumption in hardware-based machine learning (ML) systems, such as ASICs, are inaccurate and lack direct control, leading to unintended consequences and thermal issues due to sudden power surges during high performance and low latency requirements.

Innovation Solution

A hardware-based programmable architecture that directly measures power consumption using sensors and adjusts clocking signals to fit a desired power profile by throttling power and thermal performance, allowing for efficient dialing up and down of clock frequency without changing pulse width, thereby reducing power and thermal loads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If clock frequency is increased to meet high performance and low latency requirements, then processing speed is improved, but power consumption and thermal generation exceed system support

Engineering Contradiction:
Improveprocessing speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSPower

Solution Approach 1:

The system dynamically adjusts clock frequency based on real-time power consumption feedback. A power management unit continuously monitors power usage and adjusts the clock frequency of processing elements accordingly, allowing the system to operate at high speeds when power is available and reduce speed when power limits are approached, thus resolving the contradiction between maintaining high processing speed and staying within power constraints

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements a feedback mechanism where power consumption is continuously measured and used to control clock frequency adjustments. The power management unit receives power consumption data and feeds it back to adjust operational parameters, creating a closed-loop control system that automatically balances performance and power consumption without external intervention

Inventive Principle:
Principle #23Feedback

2Ease of operation

If conventional power monitoring methods are used based on chip activity inference, then power consumption can be indirectly tracked, but measurement accuracy is insufficient

Engineering Contradiction:
Improvepower monitoring capabilityVSAvoidpower measurement accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent replaces indirect inference-based power monitoring with direct electrical measurement using sensing circuits. Instead of estimating power consumption from chip activity metrics, the system uses dedicated power sense circuits that directly measure current and calculate power consumption, providing accurate real-time data for power management decisions

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Power

If clock frequency is reduced to throttle power consumption, then power usage is controlled, but unintended consequences occur in other parts of the chip

Engineering Contradiction:
Improvepower consumptionVSAvoidunintended consequences
Core Design Contradiction:
PowerVSObject-generated harmful factors

Solution Approach 1:

The system applies local quality by selectively adjusting clock frequency for specific processing elements rather than uniformly reducing frequency across the entire chip. The power management unit can individually throttle clock signals to specific blocks or tiles that are exceeding power constraints, while allowing other parts of the chip to continue operating at full speed, thus controlling power consumption without causing unintended consequences in other functional areas

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11635739B1System and method to manage power to a desired power profile
Publication Date: 2023.04.25 MARVELL ASIA PTE LTD
  • US11635739B1 patent drawing
  • US11635739B1 patent drawing
  • US11635739B1 patent drawing

AI summary

A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.