Power Profile Throttling via Clock Duty Cycle Control
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Solution Overview
Problem
Current methods fail to accurately monitor and throttle power consumption in hardware-based machine learning systems, leading to inaccurate power management and potential thermal issues due to sudden power surges, which can exceed system capabilities.
Innovation Solution
A hardware-based programmable architecture that directly measures power consumption and adjusts it to fit a desired power profile by modifying the clocking signal's duty cycle without changing the frequency, using a power measurement engine, power throttling signal generator, and power throttling engine to ensure power consumption aligns with predefined limits, while also monitoring and managing thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power consumption is increased to meet high performance and low latency requirements, then processing speed and performance are improved, but power draw and thermal generation exceed system capabilities
Solution Approach 1:
The patent applies dynamics by making the clocking signal duty cycle adjustable and variable over time. The system dynamically modifies the duty cycle of the clocking signal to control power delivery to different regions of the chip, allowing the system to adapt power consumption to performance requirements in real-time rather than using a fixed power supply configuration.
Solution Approach 2:
The patent changes the duty cycle parameter of the clocking signal to control power consumption. By varying the duty cycle (the proportion of time the clock signal is high versus low), the system can precisely control the average power delivered to processing regions without changing the clock frequency or voltage levels, thus adjusting power consumption to match performance needs.
2Use of energy by moving object
If clock frequency is reduced to throttle power consumption, then power usage is decreased, but performance and processing speed are negatively affected
Solution Approach 1:
The patent applies local quality by controlling power delivery to specific regions or blocks of the chip independently through region-specific clocking signals. Different parts of the chip can have different duty cycles applied to their clocking signals, allowing power throttling in less critical regions while maintaining full performance in critical regions, thus achieving power reduction without uniformly degrading overall processing speed.
3Device complexity
If power consumption is monitored indirectly through chip activity metrics, then monitoring is simplified, but measurement accuracy is insufficient for precise power management
Solution Approach 1:
The patent uses the clocking signal as an intermediary to control and regulate power delivery to processing regions. By inserting a clocking signal generation block between the power source and the processing blocks, the system can precisely control the timing and duration of power delivery through duty cycle adjustment, providing accurate power management without requiring complex direct power measurement and control circuits.
Data Source
AI summary
A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.