Integrated Power-Rail Capacitor Layout for Stable RFID DC Supply
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Solution Overview
Problem
Existing electronic circuits face challenges in providing a stable, low noise power supply due to the need for large capacitors, which consume significant area or add complexity and cost when used as discrete components, and conventional silicon-based ICs struggle to incorporate high capacitance dielectrics effectively.
Innovation Solution
The integration of a high-k dielectric material that serves as both the gate dielectric for FETs and provides capacitance between overlapping power rails, allowing for the formation of a capacitor in a single processing step, thereby simplifying manufacturing and reducing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large capacitor is provided between power rails to provide stable power supply, then power supply stability is improved, but circuit area is increased
Solution Approach 1:
The patent merges the capacitor function with existing circuit elements by making the capacitor plates integral with the power rails and using the gate dielectric layer as the capacitor dielectric. This integration allows the capacitor to share physical space with the FET structure, providing the required capacitance without adding separate dedicated capacitor area to the circuit.
Solution Approach 2:
The gate dielectric layer serves dual purposes: it functions as the insulating layer for the FET gate and simultaneously serves as the dielectric material for the capacitor. This multi-functionality allows a single material layer to fulfill two critical roles, eliminating the need for separate dielectric layers and reducing overall circuit area.
2Reliability
If a large capacitor is provided as a discrete component between power rails, then power supply stability is improved, but device complexity and manufacturing cost are increased
Solution Approach 1:
The capacitor is merged into the integrated circuit structure at the device level, with capacitor plates formed as integral portions of the power rails. This integration eliminates the need for separate discrete capacitor components and their associated mounting and wiring, thereby reducing assembly complexity and manufacturing cost.
Solution Approach 2:
The power rails are segmented into functional portions: some portions serve as FET terminals while other portions serve as capacitor plates. This segmentation allows the same physical structure to fulfill multiple functions within the integrated circuit, reducing the need for additional discrete components.
3Ease of manufacture
If conventional silicon-based IC manufacturing is used to provide capacitance between power rails, then manufacturing process is maintained, but manufacturing complexity is increased
Solution Approach 1:
The capacitor formation process is merged with the existing FET manufacturing process. The gate dielectric layer that is already deposited during FET fabrication is simultaneously used as the capacitor dielectric, eliminating the need for separate capacitor fabrication steps and maintaining process compatibility.
Solution Approach 2:
The gate dielectric layer is deposited in advance during the FET fabrication process, before the capacitor plates are defined. This preliminary action allows the dielectric material to be in place and ready, so that when the power rail portions are configured as capacitor plates, the capacitor structure is already complete without requiring additional dielectric deposition steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides substantial capacitance while simplifying the manufacturing process and reducing the need for separate capacitors, enhancing the robustness and noise reduction in electronic circuits, particularly in RFID integrated circuits.
Implementation Method 1
a layer or other body of dielectric material (4)... a second portion (42) of which forms, together with the first rail portion (11) and second rail portion (22), a capacitance
Data Source
AI summary
An electronic circuit is described, comprising: a first power rail; a second power rail; and a field effect transistor, FET, the FET comprising: a first terminal coupled directly or indirectly to the first power rail; a second terminal coupled directly or indirectly to the second power rail; a channel of semiconductive material connecting the first terminal to the second terminal; a gate terminal to which a voltage may be applied to control a conductivity of the channel, the channel providing a conduction path from the first terminal to the second terminal; and a gate dielectric arranged to insulate the gate terminal from the channel. The circuit further comprises a layer or other body of dielectric material, the gate dielectric being a first portion of the layer or other body of dielectric material. The first power rail comprises a first rail portion arranged on a first side of a second portion of the layer or other body of dielectric material, and the second power rail comprises a second rail portion arranged on a second side of the second portion of the layer or other body of dielectric material, the second side being opposite the first side. The second portion of the layer or other body of dielectric material separates the first and second rail portions and with the first and second rail portions provides a capacitance to the circuit.