Frontside-Backside Power Rail Intermixing for Memory Area Efficiency
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Solution Overview
Problem
Conventional memory designs suffer from area inefficiency due to the use of frontside power rails for memory cells, leading to a need for improved area efficiency in modern memory architecture.
Innovation Solution
Implementing a frontside-to-backside intermixing architecture that transitions power delivery between a frontside power network and a backside power network, using buried power rails to couple frontside and backside supply rails, thereby providing a power delivery network that avoids area penalties and optimizes power domain usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If frontside power rails are used for voltage distribution to memory cells, then power delivery to frontside circuitry is achieved, but area efficiency deteriorates due to area penalty in fabrication
Solution Approach 1:
The patent transitions power delivery from a two-dimensional frontside plane to a three-dimensional structure by routing power rails to the backside of the substrate. This dimensional change allows power distribution without occupying additional frontside area, resolving the contradiction between power delivery capability and area efficiency.
Solution Approach 2:
Instead of delivering power from the frontside to memory cells as in conventional designs, the patent inverts the approach by routing power rails to the backside of the substrate and delivering power upward to the memory cells. This inversion eliminates the area penalty associated with frontside power rail routing.
2Area of moving object
If buried power rails are used on the backside, then area efficiency is improved, but power network complexity increases due to frontside-to-backside transition requirements
Solution Approach 1:
The patent segments the power network into distinct frontside and backside domains, with the backside power network handling bulk power distribution and the frontside network handling local memory cell connections. This segmentation allows the use of simple buried power rails on the backside while maintaining overall system functionality, improving area efficiency without overwhelming complexity.
Solution Approach 2:
The patent introduces intermediate structures such as through-substrate vias and transition regions that mediate between the backside buried power rails and the frontside memory cell connections. These intermediaries simplify the transition process, reducing the effective complexity of the power network while enabling area-efficient backside routing.
3Ease of manufacture
If conventional memory designs use frontside power rails, then power distribution is simplified, but fabrication area penalty increases
Solution Approach 1:
The patent resolves the contradiction by moving power rail routing to the backside dimension of the substrate. This allows power distribution to maintain its functional simplicity while eliminating the area penalty incurred by frontside power rail routing, as the backside space does not add to the device footprint.
Data Source
AI summary
Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.