Power Rail Placement in Semiconductor Isolation Structures
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Solution Overview
Problem
In semiconductor manufacturing, the arrangement of power rails in metal layers occupies significant space, limiting the advancement of semiconductor technology and reducing response speed, as increasing the dimension of standard cells to accommodate more wiring traces is not beneficial for further process node advancements.
Innovation Solution
A semiconductor structure where the power rail is formed within isolation structures and the substrate between fins, with its top surface lower than the fins' surface, allowing it to be in the same layer as the active layer without a conduction path, thereby releasing space for wiring traces, and potentially reducing the standard cell dimension or providing more space for wiring traces under the same dimension.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the power rail is arranged in metal layer and connected to active layer through conduction path, then power supply function is achieved, but space for wiring traces is occupied and standard cell dimension increases
Solution Approach 1:
The power rail is moved from the metal layer to the isolation structure, changing its spatial dimension and layer position. This allows the power rail to coexist with active layers in the same horizontal plane without occupying metal layer space, thereby reducing standard cell dimension while maintaining power supply function
Solution Approach 2:
The power rail is segmented into multiple sections formed in different isolation structures between adjacent fins. This segmentation allows distributed power supply throughout the standard cell, reducing the need for long conduction paths and minimizing space occupation
2Speed
If standard cell dimension is enlarged to provide larger wiring trace space, then response speed is improved, but advancement to next process node is hindered
Solution Approach 1:
By relocating the power rail to the isolation structure dimension rather than the metal layer dimension, the invention frees up metal layer space for wiring traces. This enables adequate wiring trace space within standard process node dimensions, maintaining response speed while enabling process node advancement
3Ease of manufacture
If power rail top surface is at same level as fin top surface, then power rail formation is simplified, but space for wiring traces is reduced
Solution Approach 1:
The power rail top surface is positioned locally lower than the fin top surface within the isolation structure. This local quality difference allows the power rail to be formed in the lower isolation structure region while leaving the upper metal layer region available for wiring traces, resolving the space conflict
Data Source
AI summary
A semiconductor structure is provided in the present disclosure. The semiconductor structure includes a substrate, a plurality of fins on the substrate, a plurality of isolation structures on the substrate, each formed on a top surface of the substrate between adjacent fins, and a power rail formed in at least one isolation structure of the plurality of isolation structures and further in the substrate, where a top surface of the power rail is lower than a top surface of the plurality of fins.