Power Rail Via Layout in Gate Cuts for Nanosheet Isolation
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Solution Overview
Problem
The challenge in semiconductor device development is to increase process margin and prevent short-circuiting between power rail via and nanosheets/source/drain regions while scaling down devices, as existing multi-gate transistors face issues with short channel effects and current control.
Innovation Solution
A semiconductor device design that includes a power rail via formed inside a gate cut, with a gate cut extending in a horizontal direction and separating the gate electrode, and a power rail via in contact with the power rail, ensuring the power rail via is overlapped by the power rail and has a specific width configuration to prevent short-circuiting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor scaling is performed to increase device density, then device density is improved, but short channel effects worsen
Solution Approach 1:
The gate electrode is divided into multiple segments by gate cuts that extend in the first horizontal direction. These gate cuts separate the gate electrode into distinct regions, allowing independent control of different channel sections. This segmentation enables better electrostatic control over the channel, suppressing short channel effects while maintaining high device density through the multi-bridge channel structure.
Solution Approach 2:
The invention transitions from conventional planar or simple vertical multi-gate structures to a three-dimensional multi-bridge channel field effect transistor structure. The gate electrode wraps around nanosheets in a multi-bridge configuration, creating a higher-dimensional gate control geometry that enhances electrostatic control and suppresses short channel effects while enabling further scaling.
2Reliability
If power rail via is formed closer to nanosheets and source/drain regions to improve connectivity, then electrical connectivity is improved, but short-circuit risk worsens
Solution Approach 1:
The gate cut structure serves as an intermediary element between the power rail via and the nanosheets/source/drain regions. The gate cut is positioned to overlap with the power rail via, creating a physical barrier and insulating separation that prevents direct contact between conductive elements. This intermediary structure eliminates short-circuit risks while maintaining proper electrical connectivity through controlled interfaces.
3Reliability
If gate cut width is increased to prevent short-circuiting, then manufacturing reliability is improved, but device area worsens
Solution Approach 1:
The gate cut structure implements local quality by having different width characteristics in different directions. The gate cut has a first width in the first horizontal direction (providing short-circuit prevention) and a second width in the second horizontal direction (minimizing area impact). This anisotropic dimensioning optimizes the balance between reliability and area efficiency, ensuring proper isolation where needed while minimizing overall device footprint.
Data Source
AI summary
A semiconductor device includes: a base substrate; a first interlayer insulating layer disposed on the base substrate; a power rail disposed inside the first interlayer insulating layer; an active pattern extended in a first horizontal direction and disposed on the first interlayer insulating layer; a gate electrode extended in a second horizontal direction different from the first horizontal direction and disposed on the active pattern; a gate cut extended in the first horizontal direction and disposed on the power rail, wherein the gate cut separates the gate electrode; and a power rail via disposed inside the gate cut, wherein the power rail via is overlapped by the power rail.