Power-On Reset Circuit With Active Capacitor Discharge

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Solution Overview

Problem

Conventional power on reset circuits generate reset signals that are sensitive to power ascending speed and fail to discharge capacitors fully, leading to improper system functioning and potential system failures during repeated power switching.

Innovation Solution

A power detection circuit controls the discharging of capacitors in the conventional RC power on reset generating circuit, using a voltage generator, inverters, and an N-typed transistor switch to maintain a constant reset signal by charging and discharging the capacitor based on reference voltage thresholds, independent of power rising or falling speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a conventional RC structure is used for power on reset generation, then the circuit is simple, but the reset signal becomes sensitive to power ascending speed and cannot maintain constant voltage levels during repeated switching

Engineering Contradiction:
Improvecircuit structureVSAvoidreset signal stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the reset signal output is fed back to control the discharge of the capacitor. When the reset signal transitions from high to low, it triggers the capacitor to discharge completely. This feedback loop ensures that the capacitor is fully discharged before the next power ascending cycle, preventing voltage accumulation and ensuring consistent reset signal generation regardless of power ascending speed or repeated switching operations.

Inventive Principle:
Principle #23Feedback

2Ease of operation

If the capacitor discharges passively during power descending, then the circuit operation is simple, but the capacitor voltage becomes higher than power supply voltage preventing full discharge and causing system failure

Engineering Contradiction:
Improvedischarge mechanismVSAvoidcapacitor discharge completeness
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent inverts the conventional discharge approach by using an active discharge mechanism controlled by the reset signal instead of passive discharge. Rather than allowing the capacitor to discharge naturally through resistive paths during power descending, the invention uses the reset signal transition to actively control a discharge path that ensures complete capacitor discharge. This inverted approach overcomes the limitation where passive discharge cannot fully drain the capacitor when its voltage exceeds the power supply voltage.

Inventive Principle:
Principle #13The other way round (Inversion)

3Productivity

If multiple reset signals are generated consecutively, then the system responds to multiple power events, but the capacitor cannot be fully discharged leading to higher reset voltage or system failure

Engineering Contradiction:
Improvereset signal generation frequencyVSAvoidreset voltage consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by ensuring the capacitor is completely discharged before the next power ascending cycle begins. The feedback mechanism detects the reset signal transition and immediately triggers capacitor discharge, preparing the circuit for the next reset event. This preliminary discharge action prevents voltage accumulation that would otherwise occur during consecutive reset signal generation, ensuring consistent reset voltage levels and preventing system failure during repeated power switching operations.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution ensures a constant reset signal is generated, independent of power rising speed and repeated switching, and ensures complete discharge of capacitors, preventing system failures and maintaining consistent reset voltage levels.

Implementation Method 1

a capacitor 102, as well as a buffer 105. The buffer 105 comprises a Schmitt trigger 103 and an inverter 104. While the power is ascending, the power is charging said capacitor 102 via said resistor 101.

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS7816957B2Power on reset generating circuit and method thereof
Publication Date: 2010.10.19 HOLTEK SEMICON INC
  • US7816957B2 patent drawing
  • US7816957B2 patent drawing
  • US7816957B2 patent drawing

AI summary

The invention mainly relates to a power on reset signal generating circuit and method thereof wherein said reset signal remains as a constant being independent of rising or descending power or repeated switching. The power on reset signal circuit can be implemented by a conventional RC power on reset circuit together with a coupled N-type transistor switch to charge or discharge the capacitor inside the conventional RC power on reset circuit.