Power-On Reset Circuit for On-Chip Converter Startup Reliability
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Solution Overview
Problem
Existing power on reset circuits in digital integrated circuit semiconductor devices face reliability issues when the time interval between power down and power up is short, and they suffer from unwanted coupling effects due to parasitic capacitance, which affects the POR threshold voltage dynamics and static DC current absorption during stand-by mode.
Innovation Solution
The primary power on reset signal is made to reset both the reference voltage generator and the secondary power on reset signal generator, with a small junction capacitor added to compensate for parasitic capacitance, and a combination of active and passive resistances in the resistive divider to optimize stand-by current absorption without compromising dynamic response, allowing selection for different external power supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the time interval between power down and power up is short, then the device response time is improved, but the reliability of the power on reset circuit deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-charging the capacitor during the power down state through the second PMOS transistor before power up occurs. This preliminary charging ensures that when power is restored quickly, the capacitor already has some charge, reducing the reset delay and improving reliability at short power intervals
Solution Approach 2:
The patent implements beforehand cushioning by providing a backup charging path through the second PMOS transistor and capacitor combination. This cushioning mechanism ensures that even if the main charging path is too slow for short power intervals, the pre-charged capacitor provides sufficient charge to maintain reliable reset operation
2Device complexity
If parasitic capacitance is present in the circuit, then the circuit structure is simplified, but the POR threshold voltage dynamics and static DC current absorption are adversely affected
Solution Approach 1:
The patent extracts the harmful parasitic capacitance effect by introducing a dedicated compensation capacitor connected to the POR threshold voltage node. This separate compensation element allows the circuit to maintain the simple structure while actively counteracting the parasitic capacitance influence on threshold voltage dynamics
Solution Approach 2:
The patent uses an intermediary compensation capacitor as a mediator between the power supply node and the POR threshold voltage node. This intermediary component provides a controlled charging path that counteracts the unwanted parasitic capacitance effects without requiring complete redesign of the existing circuit structure
3Speed
If the power on reset circuit is designed for fast response, then the response time is improved, but the static DC current during stand-by mode increases
Solution Approach 1:
The patent applies dynamics by using PMOS transistors with gate control to dynamically enable or disable charging paths based on the power state. During stand-by mode, the transistors remain off, minimizing static current, while during power up, they activate to provide fast charging response
Solution Approach 2:
The patent implements periodic action by using the power up/down cycle to control the activation of charging paths. The transistors are periodically enabled during power up events to charge the capacitor quickly, then disabled during stand-by mode to minimize static current consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability of the power on reset circuit, particularly at short power intervals, reduces parasitic capacitance effects, and minimizes static DC current during stand-by mode, ensuring consistent POR threshold voltage dynamics across various power supply voltages.
Implementation Method 1
VDC: is an on-chip voltage down converter that converts VDDE to a stable regulated internal voltage supply (VDDI)
Implementation Method 2
a small junction capacitor added to compensate for parasitic capacitance
Data Source
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Figure 6
AI summary
A power on reset circuit for initializing at power on a digital integrated circuit comprising a first power on reset signal generator (PORE_GEN) supplied by an externally applied power supply voltage (VDDE), generating a first or external power on reset signal (PORE) during external power supply voltage (VDDE) ramp up, a reference voltage generator (REF_GEN) powered by said externally applied power supply voltage (VDDE) when enabled by said first power on reset signal (PORE) for generating a stable compensating reference voltage (VREF_VDC), a voltage down converter circuit (VDC) converting the externally applied power supply voltage (VDDE) to a stable regulated internal supply voltage (VDDI) employing said reference voltage (VREF_VDC) generated by the reference voltage generator, and a second or internal power on reset signal generator circuit (PORI_GEN) supplied at said stable regulated internal supply voltage (VDDI) and generating a second power on reset signal (PORI) conveyed to core parts of the integrated circuit for initializing them at power on, has the second internal power on reset signal generator circuit with enablement means for enabling also the second internal power on reset signal generator circuit with the first power on reset signal (PORE) together with the voltage down converter circuit (VDC). Fuse means permit optimization of dynamical responses of the two reset generators for selectably supported external power supply voltages.