Power-On Reset Circuit With Current Mirror for Low-Power Startup
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Solution Overview
Problem
Existing power-on reset circuits do not effectively limit current and consume excessive power, leading to unpredictable system states during power-up due to noise and random influences, which can result in undesirable system functioning.
Innovation Solution
A power-on reset circuit configuration utilizing a current source, switch, current mirror, resistive device, and inverter, which operates with low current and power requirements by asserting a signal until the supply voltage rises above a preselected level, initializing circuitry such as comparator outputs and flip-flops, and incorporating a current mirror to ensure controlled current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power-on reset circuits are used, then the system can be initialized during power-up, but excessive current is drawn and power consumption is high
Solution Approach 1:
The circuit dynamically changes the reset signal duration parameter based on the supply voltage ramp rate. By detecting the voltage transition characteristics during power-up, the circuit adjusts the reset assertion time to match the actual power-up conditions, ensuring reliable initialization while minimizing unnecessary current draw and power consumption.
2Reliability
If conventional power-on reset circuits are used, then the system can be initialized during power-up, but current draw exceeds specified limits at lower supply levels
Solution Approach 1:
The circuit employs dynamic current limiting that adapts to the supply voltage level during power-up. As the supply voltage ramps from zero to its final value, the current limiting mechanism dynamically adjusts its threshold, allowing sufficient current for reliable reset initialization at higher voltage levels while preventing excessive current draw at lower supply levels where current limits are more critical.
3Device complexity
If the reset signal is asserted for a fixed duration, then the initialization is simple, but it may be insufficient for slow power-up sequences
Solution Approach 1:
The circuit incorporates feedback mechanisms that monitor the supply voltage transition characteristics during power-up. Based on this feedback information about the power-up sequence speed, the circuit automatically adjusts the reset signal assertion duration. This ensures that slow power-up sequences receive adequate reset time while fast power-ups receive appropriately shorter reset durations, maintaining reliability without excessive complexity.
Data Source
AI summary
A power-on reset circuit. The power-on reset circuit includes a switch, a current source coupled between a first potential and a switch first contact; a resistive device having a resistive-device first contact coupled to the first potential; a first module coupled between a second potential and a switch second contact; a second module coupled between the second potential and resistive-device second contact; and an inverter having an inverter input coupled to the resistive-device second contact. Current through the second module mirrors current through the first module. If a first mirrored potential of the second potential present on a switch control contact is greater than a preselected value, the switch first contact is coupled to the switch second contact. Otherwise, the switch first contact is decoupled from the switch second contact.