Power-On Reset Circuit With Dual Thresholds to Prevent False Triggering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Power-On Reset (POR) circuits struggle to set a trigger voltage level close to the maximum supply voltage without being sensitive to process and temperature variations, leading to false triggering due to voltage fluctuations.
Innovation Solution
An electronic circuit comprising a flip-flop circuit and a clock comparator circuit, with a bandgap voltage reference and voltage divider, generates a reset signal that is insensitive to process and temperature variations, allowing the trigger voltage to be set asymptotically close to the maximum supply voltage without false triggering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the trigger voltage level is set close to the maximum supply voltage value, then the time interval between the supply voltage reaching the trigger value and the supply voltage reaching its maximum value is minimized, but the power-on reset signal may be falsely triggered when the supply voltage fluctuates below the trigger voltage level
Solution Approach 1:
The patent segments the voltage detection function into two independent comparator circuits: a first comparator that generates a clock signal when the supply voltage reaches a first predetermined level (close to maximum), and a second comparator that generates an enable signal when the supply voltage reaches a second predetermined level (lower than the first). This segmentation allows the system to capture the voltage transition at the optimal point without being susceptible to false triggering from fluctuations, as the enable signal acts as a gate that only allows the reset signal to be generated when both conditions are met.
Solution Approach 2:
The patent uses preliminary action by having the second comparator提前 generate the enable signal at a lower voltage level before the first comparator's trigger point. This preliminary enable signal preparation ensures that when the supply voltage reaches the first predetermined level, the flip-flop is already in the correct state to capture the transition, eliminating the need to set the trigger voltage extremely close to the maximum and reducing the time loss while preventing false triggering.
2Measurement precision
If the trigger voltage level is set close to the maximum supply voltage value, then the power-on reset signal provides accurate timing indication, but the circuit becomes sensitive to process and temperature variations causing false triggering
Solution Approach 1:
The patent divides the voltage detection range into two distinct thresholds: a first predetermined supply voltage level for the clock signal and a second predetermined supply voltage level for the enable signal. The second level is specifically set to be less than the first level, creating a voltage margin that isolates the trigger detection from process and temperature variations. This segmentation allows precise timing indication at the first level while the second level provides immunity to environmental factors.
Solution Approach 2:
The patent introduces the enable signal as an intermediary between the supply voltage and the flip-flop circuit. The second comparator acts as a mediator that monitors the supply voltage at a lower, more stable threshold and only enables the flip-flop when conditions are favorable. This intermediary layer filters out the harmful effects of process and temperature variations that would otherwise cause false triggering at the higher first predetermined level.
3Reliability
If the trigger voltage level is set to be insensitive to process and temperature variations, then false triggering is reduced, but the trigger voltage cannot be set asymptotically close to the maximum supply voltage value
Solution Approach 1:
The patent successfully resolves this contradiction by segmenting the detection function into two comparators with different thresholds. The first comparator operates at a voltage level asymptotically close to the maximum supply voltage to minimize time loss, while the second comparator operates at a lower, more stable voltage level to provide insensitivity to process and temperature variations. The combination of these two segmented functions achieves both goals simultaneously.
Solution Approach 2:
The patent uses preliminary action by having the second comparator prepare the enable signal at a lower voltage level that is insensitive to variations. This preliminary preparation occurs before the first comparator's trigger point, ensuring that when the supply voltage reaches the first predetermined level close to maximum, the system is already ready to capture the transition without loss of time, while the enable signal's lower threshold provides the desired insensitivity to environmental factors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit provides a reliable indication of when the supply voltage has reached a predetermined level, minimizing false triggers from voltage fluctuations and maintaining stability across varying conditions.
Implementation Method 1
In some embodiments an inverting input node of the clock comparator circuit is coupled to a bandgap voltage reference circuit
Implementation Method 2
the voltage divider circuit outputs a divided voltage signal from a voltage divider circuit output node, where the divided voltage signal is linearly proportion to the voltage level of the supply voltage
Implementation Method 3
A clock comparator circuit output node is coupled to a clock input node of the flip-flop circuit
Implementation Method 4
In some embodiments a D input node of the flip-flop circuit is coupled to a supply voltage
Data Source
AI summary
The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.