Power-On Reset Circuit With Schmitt Trigger for Fast Capacitor Discharge
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Solution Overview
Problem
Existing power-on reset circuits are inefficient in rapidly discharging storage capacitors in response to power supply interruptions, leading to slow response times and high power consumption, while also occupying significant integrated circuit chip area and generating false signals from minor voltage fluctuations.
Innovation Solution
A power-on reset circuit incorporating a P-channel transistor, a depletion mode transistor, and an inverting Schmitt trigger circuit, which charges and discharges a capacitor through a high resistance resistor to minimize power dissipation and prevent false triggering, using a Schmitt trigger circuit with distinct switching voltages to manage the power-on reset signal effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a prior art POR circuit uses transistors MP0 and MN0 with drain-bulk diodes to discharge capacitor C0, then the circuit structure is simple, but the discharge time is extremely long (10 or more seconds) and power consumption is high
Solution Approach 1:
The patent applies dynamics by making the discharge path dynamically controllable through the addition of transistor MP1. The transistor switches between blocking and conducting states based on the voltage at node ND, enabling rapid discharge when needed while preventing discharge during normal operation. This dynamic control resolves the contradiction by allowing fast discharge (improving speed) only when power supply interruption is detected, while maintaining high impedance during normal operation (reducing power consumption).
Solution Approach 2:
The patent introduces transistor MP1 as an intermediary element between the existing circuit components. This intermediary transistor acts as a controlled switch that enables or disables the discharge path through capacitor C0. When MP1 is turned on, it provides a low-impedance discharge path for rapid capacitor discharge; when off, it blocks the discharge path to minimize power consumption. This intermediary component resolves the contradiction by providing conditional discharge capability.
2Loss of time
If a POR circuit uses a low impedance discharge path to rapidly discharge capacitor C0, then the response time to power interruption is fast, but the power consumption increases significantly
Solution Approach 1:
The circuit dynamically adjusts the impedance of the discharge path based on operational conditions. During normal operation, the discharge path maintains high impedance to minimize power consumption. Upon detection of power supply interruption (indicated by voltage drop at node ND), transistor MP1 switches to a low-impedance state, enabling rapid discharge of capacitor C0 and fast response time. This dynamic impedance adjustment resolves the contradiction between fast response and low power consumption.
Solution Approach 2:
The circuit employs periodic monitoring of the power supply voltage through transistor MP1's gate connection to node ND. When the voltage drops below a threshold indicating power interruption, the discharge action is triggered. This periodic detection and conditional activation enables the circuit to achieve fast response only when necessary, while maintaining energy-saving mode during normal operation, thus resolving the contradiction.
3Reliability
If a POR circuit uses multiple transistors and resistors to ensure reliable power-on reset functionality, then the reliability is improved, but the integrated circuit chip area occupied increases
Solution Approach 1:
Transistor MP1 serves multiple functions: it acts as a switch for rapid discharge, a detector for power supply interruption (through its gate connection to node ND), and a controller for the discharge timing. By making this single transistor multi-functional, the patent reduces the need for additional dedicated components, thereby maintaining reliable power-on reset functionality while minimizing the increase in chip area.
Solution Approach 2:
The patent merges the discharge control function with the existing power supply monitoring function by connecting MP1's gate to node ND, which already monitors the power supply voltage through resistor R1. This merging of functions allows the circuit to detect power interruptions and trigger discharge using the same monitoring infrastructure, reducing the need for separate detection and control components, thus improving reliability without proportionally increasing chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution rapidly discharges storage capacitors, reduces power consumption to less than 100 nanoamperes, occupies minimal chip area, and avoids generating signals from minor voltage fluctuations, ensuring timely and efficient power-on reset operations.
Implementation Method 1
a second transistor (JP0) between the second supply voltage (GND) and a second terminal of the discharge resistor (R0), the second transistor (JP0) being a depletion mode transistor
Implementation Method 2
A power-on reset circuit incorporating a P-channel transistor, a depletion mode transistor, and an inverting Schmitt trigger circuit
Data Source
AI summary
A power-on reset (POR) circuit includes a first transistor (MPa) having a source coupled to a first supply voltage (VDD) and a gate coupled to a second supply voltage (GND). A resistor (R0) has a first terminal coupled by a depletion mode transistor (JP0) to the second supply voltage and a second terminal coupled to a drain of the first transistor. A Schmitt trigger (20) has an input coupled to receive a first signal (VTRIGGER) on a conductor (14) coupled to the second terminal of the resistor and a terminal of a capacitor (C0), for producing an output voltage (VO) representative of a power-on reset signal (VPOR) in response to an interruption of the first supply voltage (VDD).