Power Management Cluster Reset Path Integration for SoC Test Coverage
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Solution Overview
Problem
Existing system-on-chip (SoC) power management designs separate functional and test reset paths, leading to incomplete test coverage and inability to verify normal operation of power elements during reset tests.
Innovation Solution
A no-code approach is used to design a power management cluster where the test reset path is integrated with the functional reset path, allowing for simultaneous testing of reset functions across all power elements and IP blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate functional and test reset paths are designed, then functional mode operation is ensured, but test coverage is incomplete and power element verification is impossible
Solution Approach 1:
The patent merges the functional reset path and test reset path into a single integrated reset controller that can operate in both functional mode and test mode. The reset controller includes a mode selection mechanism that routes reset signals through the same path regardless of whether the system is in functional mode or test mode, thereby achieving complete test coverage while maintaining functional operation. This eliminates the need for separate parallel paths and their associated complexity.
Solution Approach 2:
The reset controller is designed as a universal component that performs multiple functions: it generates reset signals for functional operation, generates test reset signals for testing, and routes both types of signals through the same path. The controller includes mode selection logic that determines whether to operate in functional mode or test mode based on external control signals, making it a multi-functional component that resolves the contradiction between reliability and complexity.
2Adaptability or versatility
If separate functional and test reset paths are used, then functional mode is supported, but design resources are increased
Solution Approach 1:
Instead of creating separate reset controllers for functional mode and test mode, the patent combines both functionalities into a single reset controller. The controller includes mode selection logic that determines the operating mode based on external control signals (functional_mode signal and test_mode signal). This single unified structure reduces design resources while maintaining the ability to operate in both functional and test modes, directly resolving the contradiction between adaptability and complexity.
Solution Approach 2:
The reset controller is designed as a universal component that can perform both functional reset generation and test reset generation through the same signal path. The controller includes multiplexing logic that selects between functional reset signals and test reset signals based on the operating mode, allowing a single component to serve multiple purposes and reducing overall design complexity.
3Ease of manufacture
If manual Verilog coding is used for power management design, then design flexibility is maintained, but design time and resources are increased
Solution Approach 1:
The patent employs a power management design automation system that automatically generates Verilog code for the reset controller based on high-level design specifications. The system includes code generation modules that take design parameters (such as number of power domains, reset timing requirements) as input and automatically produce the corresponding Verilog implementation. This self-service approach to code generation significantly reduces manual coding effort and design cycle time while maintaining design flexibility through parameterized templates.
Solution Approach 2:
The patent uses pre-established design templates and code libraries for the reset controller that have been previously developed and validated. These templates include standard reset control logic, mode selection mechanisms, and test integration frameworks that can be instantiated with minimal customization. By performing the complex coding work in advance and creating reusable templates, the system enables rapid deployment of new power management designs without repeating the same manual coding efforts, thereby reducing design time while maintaining flexibility.
Data Source
AI summary
The present disclosure provides a system and method for designing a power management cluster using a no-code approach, enabling test reset delivery through the same path as a functional reset in test mode. The system includes at least one processor executing instructions stored in memory, the instructions comprising: generating a power instance from power component information; generating a reset controller instance upstream of the power instance to transmit a reset output to a target; setting first connection information between the target and the reset controller instance; generating a reset test controller instance including a test mode TDR block and a test control TDR block; setting second connection information between the reset and reset test controller instances; and generating hardware code based on the components and connection information.