Power-On Reset Circuit Using Transistor Stack Delay
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Solution Overview
Problem
Conventional power-on reset (POR) circuits in integrated circuits (ICs) face challenges in achieving desired time delays and trip level accuracy while minimizing static power consumption and footprint, especially in low-power ICs.
Innovation Solution
The proposed POR circuit utilizes a first transistor, a stack of transistors, and a logic circuit to generate a reset signal based on the ramp-up of the supply voltage, achieving the desired time delay with fewer delay elements and maintaining trip level accuracy across varying ramp-up rates and temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If conventional POR circuits use supplementary components to achieve desired time delay, then the time delay is achieved, but the overall size and complexity of the POR circuit expands
Solution Approach 1:
The patent merges the delay generation function with the voltage monitoring function by using the inherent capacitance at the gate terminal of the first transistor. This capacitance naturally delays the voltage rise at the gate terminal during power-on, eliminating the need for separate delay components while achieving the desired time delay for reliable initialization of functional circuits.
Solution Approach 2:
The POR circuit uses its own internal components (the first transistor and its gate capacitance) to generate the required delay. The gate capacitance of the first transistor itself serves as the delay element, making the circuit self-sufficient and eliminating external supplementary components.
2Duration of action of moving object
If conventional POR circuits use supplementary components to achieve desired time delay, then the time delay is achieved, but the power consumption increases
Solution Approach 1:
The POR circuit uses its own internal components (the first transistor and its gate capacitance) to generate the required delay. The gate capacitance of the first transistor itself serves as the delay element, making the circuit self-sufficient and eliminating external supplementary components.
Solution Approach 2:
The patent extracts the delay function from separate supplementary components and integrates it into the inherent gate capacitance of the first transistor. This extraction eliminates the need for additional power-consuming delay elements while maintaining the required time delay for reliable circuit initialization.
3Area of stationary object
If conventional POR circuits reduce component count, then footprint is reduced, but trip level accuracy deteriorates
Solution Approach 1:
The patent merges the delay generation function with the voltage monitoring function by using the inherent capacitance at the gate terminal of the first transistor. This capacitance naturally delays the voltage rise at the gate terminal during power-on, eliminating the need for separate delay components while achieving the desired time delay for reliable initialization of functional circuits.
Solution Approach 2:
The patent employs a stack of transistors with carefully selected threshold voltages to generate accurate trip levels. The second transistor in the stack has a threshold voltage that determines the trip level for the reset signal, ensuring accurate voltage threshold detection despite the reduced component count.
Data Source
AI summary
A power-on reset (POR) circuit includes a first transistor and a stack of transistors. The first transistor generates an enable voltage based on a first supply voltage. The enable voltage is a reduced version of the first supply voltage and ramps up based on a ramp-up of the first supply voltage. The stack of transistors generates a control voltage. The control voltage is a reduced version of the enable voltage and ramps up based on the ramp-up of the enable voltage. The control voltage delays ramping of the enable voltage such that the enable voltage ramps up to a first threshold voltage associated with the stack of transistors in a first time period. Further, a reset signal generated by the POR circuit is asserted when the enable voltage exceeds the first threshold voltage at the end of the first time period.