Power-On Reset Circuit Using Self-Referenced Threshold Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power-on reset (POR) circuits in integrated circuits face challenges in transitioning between reset states due to variations in process and temperature, requiring a fixed supply voltage and additional timing margins, which can lead to inefficiencies and instability in register state transitions.
Innovation Solution
A POR circuit that utilizes VDD/VT threshold circuitry to generate self-referenced threshold voltages based on transistor Vt, allowing for transition detection and control between POR_active and POR_inactive states, independent of the VDD ramp slew rate, ensuring stable and timely register state changes across temperature and process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a fixed supply voltage is used for POR transitions, then the POR circuit can operate with stable reference levels, but the circuit becomes sensitive to process and temperature variations requiring additional timing margins
Solution Approach 1:
The patent changes the reference parameter from a fixed supply voltage to a dynamic threshold voltage that adapts to process and temperature variations. The VDD/VT threshold circuitry generates reference voltages proportional to transistor threshold voltages, which inherently track process and temperature changes, eliminating the need for additional timing margins while maintaining reliable POR transitions.
Solution Approach 2:
The POR circuit uses self-referenced threshold voltages generated by the VDD/VT threshold circuitry, which automatically adjust to process and temperature conditions without external intervention. The circuit serves itself by using its own threshold characteristics as the reference, eliminating sensitivity to external variations.
2Reliability
If additional timing margins are added to account for process and temperature variations, then register state transitions become more reliable, but the POR circuit transitions slower and loses efficiency
Solution Approach 1:
The patent changes the reference parameter from a fixed supply voltage to a dynamic threshold voltage that adapts to process and temperature variations. The VDD/VT threshold circuitry generates reference voltages proportional to transistor threshold voltages, which inherently track process and temperature changes, eliminating the need for additional timing margins while maintaining reliable POR transitions.
3Device complexity
If the POR circuit uses fixed threshold voltages, then the circuit design is simpler, but the circuit cannot adapt to process and temperature variations
Solution Approach 1:
The patent implements dynamic parameter adaptation by generating reference voltages proportional to transistor threshold voltages. The VDD/VT threshold circuitry automatically adjusts reference levels based on process and temperature conditions, providing adaptability without significant design complexity increase.
Solution Approach 2:
The POR circuit uses self-referenced threshold voltages generated by the VDD/VT threshold circuitry, which automatically adjust to process and temperature conditions without external intervention. The circuit serves itself by using its own threshold characteristics as the reference, eliminating sensitivity to external variations.
4Stability of the object's composition
If the POR transition is delayed to ensure stability, then register state changes are more reliable, but the time to reach operational state increases
Solution Approach 1:
The patent changes the reference parameter from a fixed supply voltage to a dynamic threshold voltage that adapts to process and temperature variations. The VDD/VT threshold circuitry generates reference voltages proportional to transistor threshold voltages, which inherently track process and temperature changes, eliminating the need for additional timing margins while maintaining reliable POR transitions.
Data Source
AI summary
A power-on-reset (POR) circuit for CMOS logic is operable to transition between a POR_active state and a POR_inactive state and can include: (a) VDD/VT threshold circuitry to provide a Vtp_threshold voltage based on input Vdd and PMOS Vtp, and a Vtn_threshold voltage based on input Vdd and NMOS Vtn; (b) POR transition detect circuitry to provide a POR_transition signal (active/inactive) based on a function (Vtp, Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry to provide the POR_state signal (active/inactive) based on the POR_transition signal. For a POR out-of-reset transition, the POR transition detect circuitry to switch the POR_transition signal inactive based on the function (Vtp, Vtn) corresponding to the POR_inactive state, and the POR transition control circuitry, responsive to the POR_transition signal switching to inactive, to initiate a POR out-of-reset delay period, and to signal the POR_inactive state after the POR out-of-reset delay period.