Power-On Reset Circuit Using NMOS-PMOS Threshold Summation
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Solution Overview
Problem
Conventional power-on reset circuits in semiconductor devices rely solely on the threshold voltage of PMOS transistors for timing the reset signal switch, which can lead to insufficient reset operations due to manufacturing variations in MOS transistor threshold voltages, resulting in unreliable reset functions.
Innovation Solution
A semiconductor device with a power-on reset circuit that includes a power supply voltage monitoring circuit using both NMOS and PMOS transistors, where the reset signal is switched when the voltage of the first power supply is equal to or greater than the sum of the threshold voltages of both transistors, ensuring reliable reset operations across manufacturing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the reset signal switching timing is determined solely by the threshold voltage of PMOS transistor, then the circuit structure is simple, but the reset operation becomes unreliable due to manufacturing variations in threshold voltages
Solution Approach 1:
The patent changes the parameter used for reset signal switching from a single threshold voltage (PMOS only) to a composite parameter representing the sum of threshold voltages of both NMOS and PMOS transistors. This is achieved by using a current mirror circuit that mirrors the current through the PMOS transistor to the NMOS transistor, creating a switching condition that depends on both threshold voltages. This parameter change makes the reset operation more reliable by accommodating manufacturing variations in both transistor types.
2Ease of operation
If only PMOS transistor threshold voltage is used for reset timing, then the control mechanism is simple, but manufacturing variations cause insufficient reset operations
Solution Approach 1:
The patent implements a feedback mechanism through the current mirror circuit that continuously monitors and compares the threshold voltages of both NMOS and PMOS transistors. The current mirror circuit creates a feedback loop where the current through the PMOS transistor is mirrored to the NMOS transistor, and the reset signal switching is controlled based on the combined effect of both threshold voltages. This feedback mechanism ensures that manufacturing variations in either transistor type are compensated for, maintaining consistent reset operation across different manufacturing batches.
3Loss of time
If the reset signal switches at lower voltage (PMOS threshold only), then the reset operation starts earlier, but the reset may be incomplete due to insufficient voltage headroom
Solution Approach 1:
The patent prepares the reset signal switching condition in advance by establishing the current mirror relationship between NMOS and PMOS transistors before the reset operation is needed. The circuit is designed so that both transistors are already biased and their threshold voltages are already accounted for in the switching condition. When power is applied, the reset signal switches at the appropriate moment based on the combined threshold voltages, ensuring that the reset operation starts at the correct time with sufficient voltage headroom for complete execution.
Data Source
AI summary
A semiconductor device that outputs a reset signal for controlling a reset operation of a reset target circuit connected to a first power supply and a second power supply having a voltage lower than a voltage of the first power supply, the semiconductor device including: a power supply voltage monitoring circuit connected to the first power supply and the second power supply, the power supply voltage monitoring circuit monitors the voltage of the first power supply, wherein the power supply voltage monitoring circuit includes a first transistor having a first conductive type and a second transistor having a second conductive type different from the first conductive type, and wherein the reset signal is switched when the voltage of the first power supply is equal to or greater than a sum of a threshold voltage of the first transistor, and a threshold voltage of the second transistor.