Power-On Reset Circuit Using Voltage Difference Detection
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Solution Overview
Problem
Conventional power-on-reset circuits in integrated circuits face challenges in supporting a wide range of slew rates, brown-out reset functions, robustness, low power consumption, and cost-effectiveness due to large silicon area requirements and constant slew rates without supply brown-out reset functions.
Innovation Solution
A power-on-reset circuit design incorporating a NAND gate, inverter, charge module, voltage difference detection module, step-down module, and feedback module, utilizing PMOS and NMOS transistors, and diode-type circuits to manage voltage transitions and maintain stability across varying power supply conditions, enabling operation over a wide voltage range with different slew rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional RC delay circuit is used to delay the power supply voltage, then the reset signal can be generated, but the capacitor value must be large which requires large silicon area and increases chip cost
Solution Approach 1:
The patent changes the operating parameters of the circuit by using a voltage difference detection mechanism instead of a simple RC delay. The detection module monitors the voltage difference between VDD and VOUT, triggering the reset signal when the difference exceeds a threshold, thereby eliminating the need for large capacitor values while maintaining reliable reset signal generation.
Solution Approach 2:
The patent replaces the passive RC mechanical delay system with an active voltage difference detection system using transistors and logic gates. This substitution allows for more precise control of the reset signal timing without being constrained by physical capacitor size, significantly reducing the silicon area required.
2Adaptability or versatility
If a conventional power-on-reset circuit is used, then the reset function is provided, but it has constant slew rate without supply brown-out reset functions and cannot support a wide range of slew rates
Solution Approach 1:
The patent designs a universal power-on-reset circuit that can handle multiple functions: it supports a wide range of slew rates through its voltage difference detection mechanism and simultaneously provides brown-out reset functionality. The circuit monitors both the absolute voltage level and the voltage difference, enabling it to adapt to different operating conditions and provide comprehensive protection.
Solution Approach 2:
The patent introduces dynamic behavior to the reset circuit by continuously monitoring the voltage difference between VDD and VOUT. This dynamic monitoring allows the circuit to adapt to varying slew rates and provide appropriate reset signals regardless of the power supply ramp characteristics, enhancing both adaptability and reliability.
3Duration of action of moving object
If the capacitor value is increased to achieve proper delay, then the delay time is sufficient, but the silicon area and chip cost increase
Solution Approach 1:
The patent fundamentally changes the parameter used for delay control from capacitor value to voltage difference threshold. By monitoring when the voltage difference between VDD and VOUT exceeds a predetermined threshold, the circuit achieves sufficient delay time without requiring large capacitor values, thereby maintaining appropriate timing while minimizing silicon area.
4Adaptability or versatility
If a simple RC circuit is used, then the circuit complexity is low, but it cannot provide brown-out reset function and has limited adaptability
Solution Approach 1:
The patent designs a multi-functional circuit that integrates both power-on reset and brown-out reset capabilities. The voltage difference detection module and control logic work together to provide comprehensive power supply monitoring, enabling the circuit to detect both startup conditions and brown-out conditions, thereby achieving high adaptability with managed complexity.
Data Source
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AI summary
A power-on-reset circuit (30) includes an execution circuit (201) and a control circuit (202). The execution circuit includes a first input terminal (211) connected to a power supply (Vdd not shown), a second input terminal (212) and the first output terminal (221) each initially are at a low level (low= 0). The first output terminal (221) transitions from the low level to a high level (low to high: 0 -> 1) when the first input terminal and the second input terminal have a voltage not less than a predetermined voltage (211, 212 at high=1). The control circuit (202) includes a third input terminal (231) connected to the first output terminal (221), a fourth input terminal (232) connected to the first input terminal (211), and a second output terminal (241) connected to the second input terminal (212). The second input terminal (212) transitions from the low level to the high level when a difference between the voltage at the first input terminal (211) and the voltage at the first output terminal (221) is greater than the predetermined voltage.